高速IC電路板電磁干擾解決方案研究

Abstract

本論文針對高速電路的電磁干擾問題，討論發生的理論機制。然後針對一個實際雙模手機電路板的電磁干擾問題，呈現系統性分析的方法，以快速找出干擾來源，並對此實施防制對策。 電路電磁干擾，主要來自地彈雜訊和同步切換雜訊。高頻切換電流迴路的電感值和路徑的長度影響著雜訊發生的強度。降低迴路的電感﹙例如放大導線寬度﹚和善用高頻、低頻的去耦合電容並聯使用，可以有效降低雜訊的發生。 最後降低實際電路雜訊的手法，利用時脈訊號的FFT頻域強度，可以找出時脈和干擾雜訊的關連性，從而找出雜訊來源。針對時脈雜訊來源採行RC電路降低時脈訊號強度，從而降低雜訊。對直接由IC幅射出來的雜訊，則採用軟性吸波材(FAM)或是導電性遮蔽，可以有效降低。

In this thesis, the purpose is to study the mechanism and theory of high speed print circuit board EMI issue. And then presents a real case of a dual-mode handset as demonstration for practical EMI solving technique and procedure, The main EMI mechanism comes from Ground Bounce and Simultaneous Switching Noise (SSN). Main factors of EMI are inductance of high frequency switching current path and length of the path. Reducing the path inductance (such as by making wider PCB trace) and utilizing high frequency and low frequency de-coupling capacitor combination can both reduce the EMI strength. When solving the real case of a dual-mode handset EMI, by investigating into clock signal frequency domain data from digital scope’s FFT output, we can identify which clock signal contributing EMI output. Having identified the EMI source, we utilize RC circuit to reduce clock signal strength so as to make EMI strength lower. For direct EMI emitted from IC, we use flexible absorbing material (FAM) or conductive shielding as counter measure.