多層印刷電路板中佈線及過孔對EMI輻射的效應分析

Abstract

佈線（Layout）是PCB設計工程師最基本的工作技能之一。走線的好壞將直接影響到整個系統的性能，現今高速數位電路板(PCB)的數位信號上升/ 下降緣時間(rise/fall time) 已進入picoseconds，大多數高速的設計理論也要最終經過Layout得以實現並驗證，由此可見，佈線在高速PCB設計中是至關重要的。 多層印刷電路板通常傳輸線相當多，大多的傳輸線無法直接到達接收端，為了避開其它的傳輸線必須經過貫孔(via)來連結位於不同層的傳輸線。這些經由via換層對高頻信號而言，因傳輸線不連續性而產生電感和電容，進而造成電磁干擾(Electromagnetic interference)增加的問題。 本篇論文是利用ICS502 (PLL Clock Multiplier)產生高速的Clock，並在CLOCK輸出接上TRACE及負載來模擬實際電路線。研究分為有過孔、沒過孔和有無去耦合電容,比較電流路徑連續與不連續所造成EMI增加,以及有無去耦合電容對EMI的改善。測試結果雖然設置電容會增加PCB的容量負載，卻可以發揮預期的EMI雜訊抑制效果。

PCB layout is one of the most basic work skills of the design engineers .It affects the whole system performance. The signal rise time of modern high-speed digital circuit has reached picoseconds. Most high-speed design theory needs to be verified through the layout. This shows that the wiring in the PCB design is very important. Multi-layer printed circuit board usually has a number of transmission lines. Most of the transmission lines are almost impossible to directly reach the receiver. In order to avoid the other transmission lines, transmission lines on different layers must be connected through vias. If high-frequency signal changes layer through vias, PCB will have additional parasitic inductance and parasitic capacitance. Parasitic components will increase the electromagnetic interference. This article uses the ICS502 (PLL Clock Multiplier) to generate high-speed clock, with the output connected the trace and load to simulate real circuit. Research into the effects of through-hole vias and decoupling capacitors on the EMI characteristics are conducted. Although the decoupling capacitors increase the circuit load, but it can play the desired effect of EMI noise reduction.