完整後設資料紀錄
DC 欄位語言
dc.contributor.author張宏宇en_US
dc.contributor.authorChang, Hung-Yuen_US
dc.contributor.author荊鳳德en_US
dc.contributor.authorChin, Alberten_US
dc.date.accessioned2014-12-12T01:26:23Z-
dc.date.available2014-12-12T01:26:23Z-
dc.date.issued2010en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079567503en_US
dc.identifier.urihttp://hdl.handle.net/11536/41533-
dc.description.abstract快閃記憶體的元件密度高,讀寫速度快,資料儲存時間長,可多 次重覆抹除,是非揮發性記憶體中使用最廣泛的一種。因為成本低, 使用方便,目前已經是半導體產業中,產出最多的記憶體產品。大多 數的電子產品中,都使用快閃記憶體,低容量的應用於儲存軔體程式 或玩具,中容量的應用於網路設備和手機,高容量的則可應用於數位 相機和固態硬碟等,因為應用廣泛,產值高,所以針對快閃記憶體的 研究和改善,是相當重要的課題。 隨著半導體製程的進步,快閃記憶體細胞的感測電流已經從以往 的 100uA 降低到 0.13um 製程的 30uA 左右,可以預見隨著元件繼 續微縮,感測電流將會更小,所以任何非預期的電流,都很容易造成 讀取錯誤的情況發生,本文主要是延針對位元線漏電問題,提出適當 的設計改善方法。 傳統降低位元線漏電電流的方法,是對一整條位元線提供高電壓, 單純靠汲極端的耦合電壓來降低記憶體細胞的漏電流,近年來則多採 用針對單一字元或位元組,同時在字元線和位元線上施加高電壓,來 降低記憶體細胞的漏電流,兩種方法各有優缺點,本文嘗試整合這兩 種方式,實際應用在 0.13um 製程的64Mb 快閃記憶體上,改善位 元線漏電問題。zh_TW
dc.description.abstractFlash memory which is the most popular non-volatile memory has a lot of advantages --- high density, fast read-write, long time data-retention and multi-times erase. Because of low-cost and easy use, Flash memory becomes the dominate semiconductor product. It can be used in many electric products. People use low-density parts to keep firmware program, middle parts in network equipment and cellular phone, high-density parts in digital camera and solid-state disc, etc. That’s why Research and Development of flash memory have become very important. Following with the progress of semiconductor industry, flash cell sensing current reduce from 100uA to about 30uA in 0.13um process. In the near future, lower sensing current can be expected. It means that any unexpected leakage current may cause sensing wrong. This thesis bring up some methods to improve the bit-line leakage issue. The traditional method to improve bit-line leakage is force high voltage on whole bit-line to use cell drain coupling to reduce cell leakage. Another new method is force high voltage on both word-line and bit-line to program single word or byte to reduce bit-line leakage. There are advantage and drawback in both method, we try to combine the two methods and realize it in a real 0.13um flash product.en_US
dc.language.isozh_TWen_US
dc.subject快閃記憶體zh_TW
dc.subject字元線zh_TW
dc.subject漏電zh_TW
dc.subjectflash memoryen_US
dc.subjectbit-lineen_US
dc.subjectleakageen_US
dc.title0.13微米以下快閃記憶體位元線漏電之防治方法zh_TW
dc.titleThe Method of Reducing Flash Memory Bit-Line Leakage under 0.13um Processen_US
dc.typeThesisen_US
dc.contributor.department電機學院電子與光電學程zh_TW
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