Gigabit Ethernet 電磁干擾對策之分析

Abstract

現代的電子產品功能越來越強大，操作速度越來越快，電子線路也越 來越密集與複雜，電磁干擾(EMI)和電磁相容性(EMC)問題變成了高速數位 電路設計上的主要挑戰。

本論文主要探討網通產品之Gigabit Ethernet電磁干擾常用的電路設 計與除錯方向。針對PHY之去耦合電容、網路變壓器之高低壓側電容與I/O 之參考地處理等電磁干擾對策手法，藉由實際測試與測試結果分析，以評 估對125MHz與其它諧波250MHz、375MHz…等頻率點的EMI改善效果與影響 差異。

Modern electronic products are characterized by increasing functionality,faster operation speed, denser and more complex electronic circuits.Electromagnetic interference (EMI) and electromagnetic compatibility (EMC)problems have become major challenges in the design of high-speed digital circuits.

This thesis mainly discusses electromagnetic interference circuit design and debug direction commonly used in the design of Gigabit Ethernet networking products. Specifically, decoupling capacitors for the PHY, capacitors on both sides of network transformer, and segmentation of I / O ground are investigated experimentally to evaluate their effectiveness against EMI at the fundamental clock frequency of 125 MHz and it's harmonic of 250 MHz, 375 MHz ... etc .