THE SIGNAL DELAY IN INTERCONNECTION LINES CONSIDERING THE EFFECTS OF SMALL-GEOMETRY CMOS INVERTERS

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	SHIAU, MC	en_US
dc.contributor.author	WU, CY	en_US
dc.date.accessioned	2014-12-08T15:05:37Z	-
dc.date.available	2014-12-08T15:05:37Z	-
dc.date.issued	1990-03-01	en_US
dc.identifier.issn	0098-4094	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/31.52736	en_US
dc.identifier.uri	http://hdl.handle.net/11536/4159	-
dc.language.iso	en_US	en_US
dc.title	THE SIGNAL DELAY IN INTERCONNECTION LINES CONSIDERING THE EFFECTS OF SMALL-GEOMETRY CMOS INVERTERS	en_US
dc.type	Note	en_US
dc.identifier.doi	10.1109/31.52736	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS	en_US
dc.citation.volume	37	en_US
dc.citation.issue	3	en_US
dc.citation.spage	420	en_US
dc.citation.epage	425	en_US
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.identifier.wosnumber	WOS:A1990CZ08000013	-
dc.citation.woscount	4	-
顯示於類別：	期刊論文

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