修正蕭基位障非揮發性記憶體於薄膜電晶體基板之研究

Abstract

在本論文中，我們對於薄膜電晶體基板上具有修正蕭基位障源極/汲極之快閃記憶體進行研究。實驗試片之閘極薄膜層採用SONOS搭配p型複晶矽閘極。其源極/汲極分為純蕭基位障、修正蕭基位障、和傳統P-N接面。我們將探討不同源極/汲極結構對其記憶體特性的影響。 在Fowler-Nordheim寫入機制中，修正蕭基位障源極/汲極記憶體相對於其他結構展現較佳的寫入速度。因此，修正蕭基位障除具有低溫製程之優點，在寫入速度上亦具有其競爭力。在通道熱電子(channel hot electron)寫入機制中，修正蕭基位障記憶體元件為汲極端注入特性。未達成源極端注入造成修正蕭基位障源極/汲極記憶體有較差之寫入速度。純蕭基位障源極/汲極可達成源極端注入，但其原因乃從源極進入之電子較少，使得無法有大量源極端注入效果發生。總體來說，修正蕭基位障源極/汲極記憶體之寫入速度特性未有突破性攀升，原因為電子在被陡峭蕭基位障能帶加速時遭到通道中複晶矽之晶界(grain boundaries)干擾，使熱電子較難產生。 在Fowler-Nordheim抹除機制中，不同源極/汲極結構不影響抹除速度。在通道熱電子寫入之後，帶對帶熱電洞(band-to-band hot hole)抹除機制只有在傳統P-N接面源極/汲極有明顯抹除效果。複晶矽通道上薄穿隧氧化層之品質導致本論文中記憶體元件在儲存資料持有性上之表現較差。多次寫入/抹除之後，SONOS結構會發生抹除困難(hard-to-erase)之現象。104次寫入/抹除之後，試片普遍開始性能退化。以Fowler-Nordheim寫入時，修正蕭基位障源極/汲極記憶體元件由於會產生能量較高的電子，且儲存位置較集中於靠近源極/汲極的位置，因而相較之下其性能退化較嚴重。以通道熱電子寫入時，傳統P-N接面源極/汲極會集中於汲極端產生高能量高的電子注入，因而其性能退化較嚴重。

In this thesis, flash memory on thin film transistor (TFT) substrate with source/drain (S/D) engineering by the formation of implant to silicide (ITS) modified Schottky-Barrier (MSB) is studied. The gate stack of experiment samples are set to be SONOS with p-type poly silicon gate. S/D formation is verified into pure Schottky-Barrier (SB), MSB, and conventional p-n junction. Memory characteristics of the cells with different S/D structure are investigated both in Fowler-Nordheim (FN) and channel hot electron (CHE) programming. In FN programming, MSB S/D memory exhibits slightly better program speed than conventional S/D. Therefore, the MSB S/D shows the competitiveness since it can be formed by low thermal budget and less time consumption fabrication process. In CHE programming, MSB S/D memory has drain side injection. That the source side injection is absent leads to poor CHE program speed for MSB S/D. Pure SB S/D has the fewer supply of electrons from source so it results in weak source side injection which isn’t helpful to program efficiency. In general, the speed improvement in MSB S/D on TFT substrate is not obviously rising, even though the sharp SB band banding could accelerate electrons. The reason is that the hot electrons become more difficult to be generated since the grain boundaries in poly silicon channel disturb the acceleration of sharp SB band bending. It is found that the efficiency of FN erasing isn’t affected by S/D engineering. After CHE program, band-to-band hot-hole (BBHH) shows the erase ability only in conventional S/D. In this thesis, the poor quality of thin tunneling oxide on poly-silicon grain causes poor 10-year extrapolated charge retention. Hard-to-erase phenomenon happens in endurance characteristic since the deep level trapping in SONOS nitride layer. The memory window loss relates to the uniformity of charge storage, the generation of interface states, and the energy of election injection. In FN programming endurance characteristic, swing degradation for MSB S/D memory is larger than for conventional S/D, due to its higher injection energy. On the other hand, in CHE programming endurance characteristic, conventional S/D memory has more serous swing degradation than MSB S/D since it has local and large amount of hot electron injection at drain side.