具多閘極之修正蕭基位障電晶體及氮化鈦奈米晶粒記憶體之研究

Abstract

隨著製程技術的蓬勃發展，互補式金氧半電晶體和非揮發性記憶體不斷地成功微縮。然而，若持續在這些元件上使用傳統式的平坦結構設計，一些不可避免的問題將會愈來愈嚴重。因此，不僅在邏輯元件或是記憶體元件上，多閘極結構都已經被提出來用以改善元件的表現。在多閘極金氧半電晶體上，一種在源汲極接面設計上進行改良的修正蕭基位障源汲極接面電晶體已被提出來改善電晶體特性，除了可以提高驅動電流、降低外部阻抗，並可以保有原先蕭基位障電晶體所具備的優點，例如：增加短通道效應的免疫力及降低汲極引發能帶降低效應(drain-induced barrier lowing)。但是，到目前為止，對於修正蕭基位障電晶體來說，仍有許多富有價值性的深入分析需要被探討。在非揮發性記憶體上，浮動閘的設計已經被預測將會改良至電荷侷限儲存(charge trapping)的結構設計，例如改用金屬奈米晶粒。因此，如何將多閘極結構與金屬奈米晶粒的儲存結構設計整合在一起，亦是非常有價值性的探討。在本論文中，吾人對於多閘極修正蕭基位障電晶體之分析和多閘極氮化鈦金屬奈米晶粒記憶體之製備與特性做了深入的探討。 首先，利用測量元件的溫度效應，蕭基位障與修正蕭基位障電晶體的電流傳導機制被探討，並發現傳導機制主要受到蕭基位障的高度與長度來決定，而這些參數都會受到製程及外加電場的影響。在蕭基位障電晶體上，電流傳導在小閘極偏壓下會是由熱放射(thermionic emission)或穿透(tunneling)機制來主宰，而當在足夠大閘極偏壓下，將轉變由漂移擴散(drift-diffusion)機制主導。而在修正蕭基位障電晶體上，因為在源汲極延伸區域(SDE)有非常薄且高濃度的接面來有效地壓抑蕭基位障，因此，隨著閘極電壓增加，電流傳導機制會由熱放射至穿透轉變再轉變成漂移擴散方式來變化，而這些傳導機制的轉換點亦可以有效地用來評估修正蕭基位障接面形成的好壞。另外，這些轉換點通常發生在大於臨限電壓1 V左右的位置，代表在小閘極偏壓下，修正蕭基位障仍然存在並影響著電流傳導。 吾人並且提出了改良式外部負載方法用以萃取在修正蕭基位障電晶體上具有電壓相依性的源極端入射電阻(source injection resistance)。利用此方法分析觀察得到，在小偏壓下，此入射電阻隨(VGS-Vth-0.5VDS)增加，呈現指數等級下降，但在大偏壓下，將會停止下降並飽和在其外部串聯阻抗之值。這表示了源極端的修正蕭基位障會主宰著電流直到外加偏壓足夠大到完全壓抑此蕭基位障為止。而且，不同的熱預算的影響亦可用此方法觀察，若元件具有不足的後離子植入矽化物之(post-ITS)退火，在小偏壓下會有明顯較大的串聯阻抗。並且，此種方法亦可有效地用來判定修正蕭基位障的效率。 並且，我們亦成功製作出使用了P+高功函數多晶矽閘極和氧化鋁高介電常數阻擋層之奈米尺度的三閘極氮化鈦奈米晶粒非揮發記憶體，並探討不同的電荷侷限捕捉層設計之影響。首先，此元件具有大記憶窗口達到5.2 伏特且具有很好的耐久度表現。並且，對於不同厚度的氮化鈦沾濕層(wetting layer)、後續沉積退火(post deposition annealing)的時間和不同的阻擋層厚度對於記憶特性的影響亦有研究。此次製作出的氮化鈦奈米晶粒直徑皆小於三奈米，如此會導致強烈的庫倫阻斷效應(Coulomb blockage effect)並影響寫入/抹除速度和保存能力(retention)。並且，經過103秒的偏壓後，很小的閘極電壓擾動(gate disturbance)與讀取偏壓擾動(read disturbance)亦可以達成。 最後，在此奈米尺度三閘極氮化鈦奈米晶粒非揮發記憶體測量中，吾人在關閉反向讀取(reverse read)狀態下的源極電流上發現到一種不尋常但有趣的電流調變現象。經過不同的偏壓條件操作後，這個電流調變的現象可以回覆到原先的電流等級，並可來回操縱，表現出含有兩種狀態的可再現電阻調變現象。另外，此現象可與操作在開啟狀態下的非揮發記憶體特性合併展現出具有兩位元(dual-bit)操作方式的可能性。而且，藉由更進一步地分析其電流組成、儲存能力表現、溫度效應、元件尺寸效應(area effect) 和閘極疊層設計的影響後，吾人推測出一個可能在局部電荷侷限捕捉層產生或阻斷導電細絲(conducting filaments)而引發此電流調變現象的操作模型。 總而言之，利用變溫測量和我們提出的改良式外部負載方法，在修正蕭基源汲極電晶體上與閘極偏壓相關的電流傳導機制與源極端入射電阻分別被探討分析。多閘極氮化鈦奈米晶粒非揮發記憶體亦被實現並具有良好的特性可做為微縮之參考，並且發現了一個可重複操作的關閉電流調變現象，以及討論了其可能發生的原因。

As the technology of CMOS and nonvolatile memory continuously scale down, several unpreventable issues would be encountered on the classical planar device structure. Hence, multi-gate structure is provided to enhance the device performance either on the logic device or on the flash memory. For the multi-gate MOSFETs, modified Schottky barrier (MSB) source/drain junction are proposed to apply on the MOSFETs to improve the driving current and reserve the advantages of SB MOSFETs, such as the immunity of short channel effect and less drain-induced barrier lowing effect. However, some further analyses on the MSB MOSFETs are still required. For nonvolatile memory, the floating gate structure is projected to migrate to the charge trapping devices, such as the metal nanocrystal. Hence, the integration of metal nanocrystals and multi-gate structure is worthy to investigate. In this dissertation, multi-gate modified Schottky barrier MOSFETs and multi-gate metal TiN nanocrystal memory are investigated. The current transportation mechanisms of the SB and MSB source/drain MOSFETs are investigated firstly. By measuring the temperature effect, it reveals that the current transportation mechanism is mainly dominated by the length and height of SB, which depends on the processes and the external supplying electric-field. For SB MOSFETs, the current transportation mechanisms start from the tunneling or thermionic emission at low gate bias and eventually become to the drift-diffusion at sufficient high gate bias. For MSB MOSFETs, since the source-side SB is suppressed by the ultra-thin and highly doped SDE, the current transportation mechanism changes from the thermionic emission to tunneling and then to drift diffusion as the gate voltage increases. Moreover, the changing point of mechanism is a good indicator to evaluate the efficiency of MSB junction. In addition, the changing point of mechanism is around at VG-VTH = 1 V, indicating the MSB still exists at low gate bias condition. Then, the modified external loading method is proposed to extract the bias-dependent source injection resistance of the MSB source/drain MOSFETs. The injection resistance is observed to exponential proportion to the (VGS-Vth-0.5VDS) at low electric field but saturates to the source/drain resistance of conventional MOSFET at sufficient high electric field, suggesting the source-side MSB would dominate the current flow until the external bias large enough to suppress the barrier. The effect of the thermal budget of MSB process on the source injection resistance can observe. Sample without sufficient post-ITS annealing exhibits much higher RSD at low bias region. Moreover, this method also provides a good method to evaluate the efficiency of MSB junction. The charge trapping layer engineered nano-scale tri-gate TiN nanocrystal memories with high-k Al2O3 blocking layer and high work function P+ gate electrode are successfully fabricated and investigated. Large memory window equals to 5.2 V and good endurance performance are achieved. Memory characteristics of various samples with different TiN wetting layer thickness, post deposition annealing time, and blocking oxide thickness are also investigated. The TiN nanocrystals are smaller than 3 nm, which induces strong Coulomb blockade effect to influence the P/E speed and retention property. Furthermore, the gate disturbance and read disturbance are also measured with very small charge migrations after 103 sec. stressing bias. Finally, an abnormal but interesting current modulation is observed in the off-state source current at reverse read on the nano-scale tri-gate TiN nanocrystal memory. By different pulse bias conditions, this current modulation can switch back and forth, showing a reproducible resistive switching behavior with two different states. Possible dual-bit operation is demonstrated. From the further analyses on the current components, the retention properties, the temperature effect, the area effect, and the engineering of gate stacks, a possible switching model is supposed due to the generation and rupture of the conducting filaments in the local charge trapping layer. To summarize, the current transportation mechanism and the bias dependent source injection resistance of the MSB MOSFETs are investigated by measuring the temperature effect and our provided modified external loading method, respectively. The multi-gate SAMOS-type TiN nanocrystal nonvolatile memories are realized and an interesting repeatable current modulation is demonstrated and the possible reason is discussed.