隨機電報訊號量測法應用於前瞻CMOS元件應變技術引致的汲極電流不穩定性之研究

Abstract

近年的可靠度研究中，施加應變會對CMOS元件造成的熱載子退 化。對於n型MOSFET元件，介電層覆蓋式(CESL)元件(為單軸應變) 有較佳的可靠度、性能表現和簡易的製程。而SiC在S/D 的結構提供 了高的驅動電流。在p型MOSFET 元件中，單軸的應變結構SiGe在S/D 及嵌入式擴散阻擋層(EDB)，有著良好的可靠度和效能。 本論文中，我們利用汲極電流隨機電報訊號量測法，觀察在前瞻 應變矽元件，不同的應變技術所造成的缺陷以及可靠度的分析。首 先，在應變n型及p型MOSFET元件中，經熱載子加壓後，造成的電流 衰退，並在汲極端產生缺陷，此缺陷捕捉及釋放通道的載子，造成汲 極電流的不穩定性。藉由載子的捕捉和釋放時間進行統計分析，可以 獲得缺陷的特性。此外，透過單軸應變n型及p型MOSFETs 元件，我 們探討了不同方向的應變技術所引致的汲極電流不穩定性。 從萃取出的電流振幅並加以正常化(normalized drain current ii amplitude)進而觀察垂直應變和水平應變技術對於熱載子破壞所造成 的退化影響。相較於對於SiGe S/D結構，介電層覆蓋式(CESL)元件 中，此覆蓋層會在閘極介電層中額外的垂直應變結構，經熱載子破壞 後會引致額外的載子散射現象；而SiGe只提供在S/D方向的壓縮應 變，對於可靠度沒有額外的影響。最後，我們亦將此方法應用在SiC S/D結構元件上，因SiC亦只提供S/D方向的張力應變，無額外的應變 在介電層中，此實驗結果可加以驗證之前的結果，與SiGe S/D結構類 似，亦即其通道的應變效應，對於可靠度沒有額外的影響。

Recent study on the reliability issues, the strained devices show a higher impact ionization rate, i.e., the device degradation is proportional to the current enhancement. For n-MOSFET devices, CESL (contact etching stop layer) strain (uniaxial) is much better in terms of reliability, performance, and process simplicity; SiC on source and drain structure shows high driving current ability. For p-MOSFET device, uniaxial structure with SiGe on source and drain with EDB (embedded diffusion barrier) seems to be promising in terms of its performance and reliability. In this thesis, the hot-carrier stress induced oxide traps and its correlation with enhanced degradation in strained CMOS devices have been reported. First, the ID-RTN (Drain Current Random Telegraph Noise) has been employed to study the stress induced slow traps in uniaxial strained n-MOSFETs and p-MOSFETs. The carrier trapping and detrapping effect in the gate dielectric can be observed. The drain current fluctuation is at low level when carrier is trapped and is at high level when carrier is detrapped. Through statistically extracting and calculating the capture and emission time, we can figure out the trap properties. Secondly, different process-induced strain effect for n-MOSFETs and p-MOSFETs has been observed respectively. By extracting the normalized drain current amplitude from the drain current spectra, experimental results show that the vertical compressive strain generates extra oxide defects and induces more scattering after HC stress in CESL device. This vertical strain in CESL also contributes to a non-negligible amount of extra devices degradation. While, SiGe S/D on p-MOSFET device shows different behavior in that the compressive strain along the channel shows no impact on its reliability. The process induced strain among different strained techniques can be investigated by the ID-RTN measurement. Furthermore, the application to the study of the strained SiC on S/D has also been demonstrated. Results also show that the uniaxial strain in such device exhibits less impact on the device reliability. Therefore, this strained SiC device is similar to the SiGe S/D device in terms of the ID-RTN characteristics.