應用於超寬頻系統之低功率、高線性度射頻接收器

Abstract

本篇論文利用到複數轉導分析方法，對電晶體提出轉導等效小訊號電路模型，藉由此分析方法應用於多閘級電晶體架構之線性度分析，相較於之前所提出的分析方法，在此複數轉導分析下可以提供寬頻的線性度提升特性，以利於改善寬頻放大器電路之線性度。根據此種分析方法，超寬頻放大器與前端接收電路分別經由晶片製作來驗證。 第一顆晶片應用於超寬頻系統之-5dBm之輸入第三階交會點超寬頻放大器利用到複數導數相消技術。量測結果顯示此一超寬頻放大器在線性度方面具有5dBm 以上的提升，同時不用消耗多餘的功率。這顆超寬頻放大器在8.26mW功率損秏下，具有8.1dB之轉換增益，8dB之輸入反迴損秏以及-5dBm以上之輸入第三階交會點。 在第二顆晶片中，設計一個應用於超寬頻系統之低功率、高線性度前端接收端電路，此接收器電路包含了一個低雜訊放大器，一個主動相位分離器以及一個直接降頻混頻器。 模擬結果顯示此前端電路有20.3dB的轉換增益，10dB之輸入反迴損秏以及-4.7dBm之輸入第三階交會點，此外，此電路消秏功率為10.4mW。

A compact equivalent circuit using a complex transconductance analysis is proposed for linearity design in the multiple gated transistors configuration. This complex transconductance analysis gives broadband linearity improvement in the common source amplifier as compared to previous published analysis. Following the complex transconductance analysis, an UWB LNA and an UWB RF front-end circuit were verified through two individual chips. In the first chip, -5dBm IIP3 UWB low noise amplifier using complex derivative cancellation technique is analyzed and designed for ultra-wideband system. Measurement results show that the improvement of the linearity is more than 5dB without extra power consumption, and the designed LNA has conversion gain of 8.1dB, input return loss of 8dB, and input third-order intercept point (IIP3) of -5dBm with 8.26mW power dissipation. In the second chip, a low power and high linearity UWB receiver intends to use in the receiver path of the ultra-wideband system. This front-end circuit is composed of a low noise amplifier, an active balun, and a direct down-conversion mixer. Simulation results show that the circuit has conversion gain of 20.3dB, input return loss of 10dB, IIP3 of -4.7dBm, while consuming only 10.4mW.