隨機電報訊號量測於高閘極介電層N通道金氧半電晶體汲極電流波動之探討

Abstract

隨著互補式金氧半電晶體(CMOS)的微縮，隨機電報訊號對元件產生劇烈的汲極電流波動所造成的影響是極為重要的可靠度議題之一。 隨機電報訊號的產生是由於單一載子從基板穿隧至閘極氧化層而被捕捉的物理現象。在本篇論文中，我們可以觀察此種缺陷的物理特性並利用改良的萃取方法去準確得知缺陷的能階以及深度。

高閘極介電層元件已經廣泛的被深入研究為了去克服眾多的問題，例如閘極費米能階釘札效應(Fermi level pinning)。此現象可被追溯到高閘極介電層中氧空缺陷阱的存在。利用改良的萃取方法，可以得知缺陷在氧化層中的能階。此方法的有效性可以用隨機電報訊號的溫度相關性來驗證。本篇論文運用隨機電報訊號來觀察二種不同的缺陷，包括製程產生的缺陷、元件經過正偏壓溫度不穩定性(PBTI)伴隨的熱載子(Hot Carrier)破壞之後產生的缺陷。我們觀察到其中一顆製程產生的缺陷造成的汲極電流波動高達百分之五十。因此，CMOS電路的操作會隨著劇烈的汲極電流波動而受到影響，例如：差動放大器的電流不匹配效應。以往的文獻, 經過不同電壓破壞之後產生的缺陷多半位於氧化層和矽基板的界面，而且其汲極的電流波動相當的小，約略只有百分之一左右。在高閘極介電層元件觀察正偏壓溫度不穩定性(PBTI)伴隨的熱載子(Hot Carrier)破壞之後產生的缺陷位於高介電係數氧化層中而且其汲極的電流波動是以往文獻所觀察到的數倍。以Fowler-Nordheim (FN) 和熱載子(Hot Carrier)破壞之後產生的缺陷其汲極電流波動衰減的幅度兩者相近，然而Fowler-Nordheim (FN) 破壞產生的缺陷深度比較深。這是因為在高閘極介電層元件中，正偏壓溫度不穩定性(PBTI)伴隨的熱載子(Hot Carrier)破壞所產生的缺陷產生隨機電報訊號的位置靠近源極端，因此對汲極電流波動衰減的影響會比較輕微。無論是哪一種缺陷，載子的數量變化只占隨機電報訊號所產生振幅波動的百分之十。然而缺陷位於較深的高介電係數氧化層，所以Percolation theory被認為是主要的汲極電流波動原因，而非缺陷產生的庫倫散射造成的遷移率下降所影響。除此之外,我們利用電流隨機電報訊號對高介電係數氧化層和傳統氧化層來所作比較。相較之下，不同電壓破壞之後產生的缺陷其高介電係數氧化層的汲極電流波動其衰減的幅度較小。因此，較小的汲極電流波動衰減是因為高介電係數氧化層造成較輕微的屏蔽效應所導致。

在高閘極介電層元件中，我們首次發現正偏壓溫度不穩定性伴隨的熱載子破壞之後產生的缺陷產生明顯的隨機電報訊號現象。劇烈的汲極電流波動以及其較緩慢的衰減幅度對互補式金氧半電晶體的操作有著極大的衝擊。隨著CMOS元件技術持續的演進，高介電係數氧化層將愈形重要。本論文利用改良式的萃取缺陷深度以及能階位置的方法，可以深入了解缺陷捉放電子的行為，對於如何利用高介電係數氧化層的CMOS元件設計兼具可靠性以及性能上的優越表現可提供重要的設計參考指標。

As CMOS devices scaling down, the influence of Random Telegraph Noise (RTN) is one of the important reliability issues due to the large fluctuation of drain current. The RTN results from the single trapped carriers tunneling between the substrate and the gate dielectrics. In this thesis, we can observe the physical properties of single trapped carriers by an improved extraction and determine the trap location and the depth of traps caused by the process and by the stressed-induced traps in the high-k gate dielectric nMOSFET devices.

High-k gate dielectrics have been intensively investigated to overcome many problems such as Fermi level pinning of the gate electrode. It can be traced to the existence of oxygen vacancies in the high-k gate dielectrics. We derived an accurate form of the trap energy level using an improved extraction as mentioned. It can also be verified the validity from temperature dependent of RTN. This work is focused on two types of traps, including the Process Induced Traps (PITs) and the Positive Bias Temperature Instability (PBTI) associated hot carrier Stress Induced Traps (SITs). One of the process induced change in RTN amplitude for the high-k dielectrics was up to 50 %. Thus, the CMOS operation was affected by the severe digital fluctuation of the drain current such as mismatch of drain current for differential amplifiers. In reported papers, the trap positions of the SITs were located near the Si/oxide layer interface and the RTN amplitude of drain current was quite small below 1%. We observed that the locations of PBTI associated hot carrier SITs in the high-k dielectrics were found to be located in the bulk of high-k layer and the SITs possessed larger RTN amplitude of drain current about several times than ever reported. The ΔId/Id of the Fowler-Nordheim (FN) SIT had almost the same amount comparing to the ΔId/Id of the Hot-Carrier SIT at the same overdrive voltage, however the depth of the FN SIT was much deeper than the Hot-Carrier SIT. It can be explained that the locations of PBTI associated hot carrier SITs in the high-k dielectrics were located near the source region as RTN occurred so that it attributes to the fluctuation of drain current slightly. No matter what kinds of induced traps were, the number fluctuation was merely about 10% of all ΔId/Id fluctuation. Nevertheless, the positions of the traps were almost far away from the interface of Si/interfacial layer, the percolation theory was obviously considered to be the dominant factor of ΔId/Id fluctuation, not the mobility fluctuation. Besides, we have investigated RTN amplitude in high-k nMOSFETs in comparison with that in SiO2 nMOSFETs on SITs. It was also found that the reduction of the RTN amplitude by the surface electrons was smaller in high-k dielectrics layers, comparing to the SiO2 n-MOSFETs. Thus, it can be considered that the higher dielectrics constant leads to the small reduction of RTN amplitude resulting from slight screening effect.

As a consequence, it was found for the first time that PBTI associated hot carrier SITs cause apparent RTN phenomenon. The dramatic fluctuation of drain current and smaller reduction of the RTN amplitude has great impact on the device operation. It is necessary to understand the behaviors of these slow traps in the high-k dielectrics such that we may understand how to improve the performance and reliability of the high-k gate dielectrics devices. All the results in this thesis will be valuable to provide a design guideline for the design of advanced CMOS devices with both improved performance and reliability.