利用順向基極偏壓設計之低功耗低雜訊放大器

Abstract

本論文利用RF CMOS製程分別設計了應用於無線接收端之超低功耗和超寬頻低雜訊放大器。內容主要實現了兩個電路晶片。一個是超寬頻低雜訊放大器，另一個是次0.2毫瓦低功耗低雜訊放大器。其中對於使用三階帶通濾波器的超寬頻低雜訊放大器而言，頻寬範圍為3.1~10.6GHz，並利用順向基極偏壓技術來達成低功率消耗。輸入匹配利用三階帶通濾波器搭配源極電感來達成標準50歐姆寬匹配。此電路利用台積電0.13微米 RF CMOS 製程來實現。對於目標3.1~10.6GHz頻段內，量測結果顯示，當供應電壓0.9伏特時，整體功率消耗約8.4毫瓦，在3.3 ~ 8.1GHz頻段內，增益為10.8 ~ 5 dB，雜訊指數為3.9 ~ 4.1 dB，輸入端反射係數和輸出端反射係數皆分別小於 -6.7dB和 -5.8dB，而S12皆小於 -27.3 dB。此超寬頻低功耗低雜訊放大器的功率消耗能有效降低主要是利用對電晶體使用順向基極偏壓技術來降低臨界電壓進一步降低VDD來達成。 對於超低功耗低雜訊放大計設計而言，採用UMC90奈米製程來實現利用順向基極偏壓設計之低功耗低雜訊放大器。此電路採用串疊式架構，並將放大級電晶體M1偏壓在次臨界區域搭配使用順向基極偏壓來達成次0.2毫瓦低功耗低雜訊放大器設計。在電感模型可信之前提下，利用順向基極偏壓可將操作電壓降低至0.18V時仍能提供足夠增益。由模擬結果得到，在1.4GHz時增益(S21)大小為11dB，此時操作電壓為0.18V，功率消耗為0.19毫瓦。同時也讓雜訊指數為2.3dB，在1.5GHz時有最小雜訊指數2.1dB。在1.4GHz下，輸入逆向損耗(S11)和輸出逆向損耗(S22)分別為 -10.4dB和 -10.5dB，逆向隔離(S12)為-15.2dB。實際量測結果由於實際電感特性太差而不如預期。若將操作電壓提升至0.5伏可改善這個問題。此時增益為5.5dB而功率消耗為1.75毫瓦，S11和S22分別為 -12.1dB和 -14.8dB，而S12為-23.5dB。

In this thesis, low-power low noise amplifiers (LNA) design and fabrication have been realized using RF CMOS technologies for applications in ultra-low power or ultra-wide band (UWB) wireless receivers. The major achievements are composed of two circuit chips. One is UWB low-power LNA, and the other is sub-0.2mW ultra-low power (ULP) LNA. For the UWB LNA adopting three-section band-pass Chebyshev filter, the bandwidth can be extended over 3.1~10.6 GHz , and low power is achieved by using forward body bias (FBB) technique. The input matching to standard 50 □□ was realized through the three-section LC networks adopted in the MOS transistor with inductively degenerated source. This UWB LNA is fabricated in a 0.13-□m RF CMOS process. The measured performance over the targeted bandwidth of 3.1~ 10.6GHz indicates that the power gain is 10.8 ~ 5 dB, noise figure is 3.9 ~ 4.1 dB, power consumption is 8.4 mW from 0.9V, the input and output return losses, i.e. S11 and S22 are below -6.7dB and -5.8dB respectively, and the leakage S12 can be kept below -27.3 dB in 3.3 ~ 8.1GHz. The power consumption for this UWB LNA can be effectively reduced by lowering the supply voltage VDD attributed to substantially lower threshold voltage (VT) under forward body biases. As for the ultra-low power LNA design in part two, FBB scheme was implemented in this work using 90nm low leakage (LL) CMOS process. As a result, Sub-0.2mW LNA can be realized based on a cascade topology, in which the MOSFET at transconductance stage is biased under subthreshold condition and applied with FBB. Assuming the availability of on-chip inductors with performance predicted by the model, the VDD can be pushed to as low as 0.18V and sufficient gain can be maintained, attributed to FBB. ADS simulation predicted that this ULP LNA can attain power gain of 11 dB at 1.4GHz and consume extremely low power of 0.19mW from 0.18V. Furthermore, the noise figure (NF50) can reach the minimum of 2.1 dB at near 1.5GHz and keep around 2.3 dB at 1.4GHz. The input and output return losses (S11 and S22) are –10.4dB and –10.5dB, respectively. The port-to-port leakage (S12) is maintained as low as –15.2 dB. The power gain (S21) measured from the real chips under 0.18V is abnormally low, due to poor inductors performance and the resulted severe deviation in input matching. When increasing VDD to 0.5V, this problem can be solved and promisingly good results can be realized. The power gain (S21) is 5.5 dB at 1.4GHz and power consumption is 1.75mW from 0.5V. S11 and S22 are –12.1dB and –14.8dB, respectively, and S12 is as low as –23.5 dB.