電感耦合式電漿氮化和氟化製程對鉿系介電質薄膜之影響

Abstract

使用二氧化矽當作閘極介電層已經達到科技和理論的極限。在4Gbit動態隨機存取記憶體中的等效氧化層厚度，將被微縮到0.22奈米，此厚度非常接近二氧化矽的結構限制，因為二氧化矽的Si–O鍵長為0.17奈米。對於MOSFET閘極介電層而言，使用氧化鉿是目前及未來最為推廣的材料，但是high-k閘極介電層在C-V曲線中被發現有磁滯現象，此現象會導致MOS元件中平帶電壓漂移以及臨界電壓的不穩定。本研究製造了Al-Ti-HfAlO(HfO2)-Si 金屬絕緣層矽結構之電容，作為分析的樣品。本研究藉由探討鉿系介電質薄膜在不同電漿處理的條件下C-V和J-V的特性。此外，本研究亦探討鉿系介電質薄膜在不同氮化和氟化電漿製成的條件下之可靠度問題，諸如磁滯現象、應力引致漏電流、常壓應力測試，因此，本研究發現氮化和氟化電漿能有效的消滅氧的空洞，以及改善介面限補電荷密度，來有效的降低漏電流，改善其電容值及增加其可靠度。

Silicon oxide gate dielectric is now being pushed to both its technological and theoretical limits. The equivalent oxide thickness (EOT) in the 4-Gbit generation dynamic random access memory (DRAM) will be scaled down further to 0.22nm which is very close to the structural limit of silicon dioxide, as the Si–O bond in silicon oxide is 0.17 nm. The oxide of using Hafnium-based is a most promising material for future MOSFET gate oxide applications. Unfortunately, for high-k gate dielectrics, there is a hysteresis phenomenon in its capacitance-voltage (C-V) characteristics. This hysteresis induces a flatband voltage shift, and threshold voltage instability when it is applied to MOSFETs. In this study, we fabricated Al-Ti-HfAlO(HfO2)-Si MIS capacitor as our analysis device. The electrical characteristics of the film under different plasma conditions were discussed by C-V and I-V curves. Moreover, the reliability of the films under different plasma treatment conditions were discussed by hysteresis effect, SILC ( Stress Induced Leakage Current ) profile, CVS ( Constant Voltage Stress ) test. Hence, the nitrogen atoms and fluorine atoms can eliminate oxygen vacancies and repair the interface trap densities to suppress the leakage current.