應用於射頻發送端之低功率電路

Abstract

由於射頻前端(RF front-end)電路是整個收發機中比較耗電的部份，生物電子醫療設備或3C產品…等，對低消耗功率的需求越來越高，為了讓可攜式監控系統或3C產品有更長的電源更換周期，讓有限的資源做充分利用，因此，本論文中利用TSMC CMOS 180 nm製程來實現兩個在射頻發送端之低功率電路。 第一個電路為三倍頻器電路，利用主頻率電流相互抵消的機制，來提供超過35 dB的諧波抑制比(Harmonic Rejection Ratio)。在消耗功率為11.5 mW下有-4.2 dB 的電壓轉換增益，其電源供應為1.8 V，頻率為1.5 GHz。另外，此三倍頻在輸入與輸出皆為四相位訊號，因此，可以使用在通訊系統中之I/Q鏡像抑制(image rejection)。 另一個電路為低功率D類放大器，利用Outphasing (或 LINC)的技術，來改善傳統功率放大器線性度與效率無法同時兼得的瓶頸，根據模擬結果，在1.2 V電壓供應下，頻率為1.4 GHz時的功率消耗為14 mW，以及在1 dB壓縮下之汲極效率與PAE分別為38% 以及 29%，而系統的平均功率為33.16%

The implantable biomedical devices and portable 3C equipments necessitate low power consumption to lengthen the battery lifetime. In this thesis, two low-power circuits in RF transmitter front-end are realized and designed using TSMC 180 nm CMOS technology. The first topic is a frequency tripler with fundamental cancelling which provides more than 35 dB harmonic rejection ratio. The voltage conversion gain is -4.2 dB under 11.5 mW dynamic power consumption. In addition, this frequency tripler features quadrature signal both at input and output, it therefore can be used in communication systems which require I/Q signals for image rejection. The other topic is an outphasing power amplifier which deals with the trade-off between linearity and efficiency. The circuit is implemented by a pair of class-D power amplifiers and a transformer. According to simulation results, the power consumption is 14 mW under 1.2 V supply voltage at 1.4 GHz input frequency. The drain efficiency and power added efficiency (PAE) achieve 38 % and 29 % at input 1-dB compression point, and the average efficiency is 33.16%.