A 11-mW Quadrature Frequency Tripler with Fundamental Cancellation

標題:	A 11-mW Quadrature Frequency Tripler with Fundamental Cancellation
作者:	Tsai, Chien-Chung Chang, Derric Chen, Huan-Sheng Kuo, Chien-Nan 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
關鍵字:	frequency tripler;doubler;harmonic rejection ratio;sub-harmonic mixer
公開日期:	2010
摘要:	A low-power quadrature frequency tripler is designed by using the sub-harmonic mixer configuration. The circuit is implemented in CMOS 0.180um technology. The frequency tripler consumes 11.5mW, while the output buffers consumes 43.1mW, all with supply voltage of 1.8V. The fundamental Harmonic Rejection Ratio (HRR(1)) achieves more than 35dB, and the conversion gain achieves -4.2dB at output frequency of 4.5GHz. The entire chip area occupied 1.4x1.1 mm(2).
URI:	http://hdl.handle.net/11536/26987 http://dx.doi.org/10.1109/SMIC.2010.5422967
ISBN:	978-1-4244-5456-3
DOI:	10.1109/SMIC.2010.5422967
期刊:	2010 TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS
起始頁:	100
結束頁:	103
顯示於類別：	會議論文

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