A 11-mW Quadrature Frequency Tripler with Fundamental Cancellation

doi:10.1109/SMIC.2010.5422967

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Tsai, Chien-Chung	en_US
dc.contributor.author	Chang, Derric	en_US
dc.contributor.author	Chen, Huan-Sheng	en_US
dc.contributor.author	Kuo, Chien-Nan	en_US
dc.date.accessioned	2014-12-08T15:39:32Z	-
dc.date.available	2014-12-08T15:39:32Z	-
dc.date.issued	2010	en_US
dc.identifier.isbn	978-1-4244-5456-3	en_US
dc.identifier.uri	http://hdl.handle.net/11536/26987	-
dc.identifier.uri	http://dx.doi.org/10.1109/SMIC.2010.5422967	en_US
dc.description.abstract	A low-power quadrature frequency tripler is designed by using the sub-harmonic mixer configuration. The circuit is implemented in CMOS 0.180um technology. The frequency tripler consumes 11.5mW, while the output buffers consumes 43.1mW, all with supply voltage of 1.8V. The fundamental Harmonic Rejection Ratio (HRR(1)) achieves more than 35dB, and the conversion gain achieves -4.2dB at output frequency of 4.5GHz. The entire chip area occupied 1.4x1.1 mm(2).	en_US
dc.language.iso	en_US	en_US
dc.subject	frequency tripler	en_US
dc.subject	doubler	en_US
dc.subject	harmonic rejection ratio	en_US
dc.subject	sub-harmonic mixer	en_US
dc.title	A 11-mW Quadrature Frequency Tripler with Fundamental Cancellation	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/SMIC.2010.5422967	en_US
dc.identifier.journal	2010 TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS	en_US
dc.citation.spage	100	en_US
dc.citation.epage	103	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000281614000026	-
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