標題: | A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition |
作者: | Chen, Wei-Zen Lu, Tai-You Wang, Yan-Ting Jian, Jhong-Ting Yang, Yi-Hung Chang, Kai-Ting 交大名義發表 電子工程學系及電子研究所 National Chiao Tung University Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Harmonic mixer;PLL;RSSI;tripler |
公開日期: | 1-六月-2014 |
摘要: | A 160-GHz frequency-translation PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating a frequency tripler for frequency down conversion. A transformer-based VCO is utilized to alleviate capacitive and resistive load associated with varactor and succeeding buffer stages. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatic frequency sweeping and fast locking. Fabricated in 65 nm CMOS technology, the chip size is 0.92 mm(2). The PLL locking time is less than 3 mu s. This chip drains 24 mW from a 1.2 V power supply. |
URI: | http://dx.doi.org/10.1109/TCSI.2013.2295016 http://hdl.handle.net/11536/24700 |
ISSN: | 1549-8328 |
DOI: | 10.1109/TCSI.2013.2295016 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
Volume: | 61 |
Issue: | 6 |
起始頁: | 1648 |
結束頁: | 1655 |
顯示於類別: | 期刊論文 |