應用於寬頻傳輸線路之損耗補償技術

Abstract

隨著製程的不斷進步，積體電路的操作頻率跟著不斷提高，同時為了滿足數位通訊系統不斷增大的訊號頻寬的要求，載波的頻率跟著不斷得提升。訊號連接線普遍的存在各種系統中。在特定某些情況之下，連接線限制了整個通訊系統的速度。在這總種的高速傳輸的需求之下，提出一個針對訊號傳輸的線的損耗補償技巧是非常有價值的。另外，在一些特定的應用領域，常會用到多級的電感、電容等離線元件來實現俱有高群延遲的延遲線，針對此種應用的架構，常常伴隨著極高的損耗，損耗補償技巧在這種情形之下，更顯不可或缺。 我們實作了二顆 IC 以驗証我們所提出來的方法的正確性與其實作上的可行性。第一顆IC 是應用損耗補償技巧而實現的寬頻延遲線，在同一個IC 中，另包含了一組未經損耗補償的延遲線以當作對照組。第二顆IC 是一個多用途的RF 運算單晶片，我們可以用它來組合出相位陣列系統。以上二顆IC 都是用TSMC 65 奈米的CMOS 製程所實作。 在第一顆IC 中，我們實作了二條延遲線，損耗補償電路被安插在構成傳輸線的各級電感間，與電容做並聯。未經損耗補償的傳輸線相對於經過損耗補償的後的傳輸線在20GHz 以內的最大損耗分別是-8dB 與-3.1dB。我們花了額外的30mW 來達到這樣的改善。第二顆多用途的RF 運算單晶片，乃是由離散式放大器加以經過損耗補償的傳輸線，以及諸多可調增益級與合併能量級。同樣的，我們在同一顆IC 中實作了對稱的二股以上所提的架構。實務上，兩股都可以用來傳輸RF 訊號，並可以進一步透過數位控制碼來決定各別的RF 路徑所經的延遲長度。此外，最終的RF 訊號輸出可以是彼此混頻並降頻或是各別直接輸出。只要組併多個RF 運算單晶片，我們可以對各個路徑設定特定的延遲量，如此一來，我們將可以實作出任意單元數的相位陣列系統。

As the process node is being pushing more and more advanced, the operating frequency of integrated circuits rise at an astonishing rate. Also to keep up with the tremendous need on increasing data transmission bandwidth, carrier frequency of communication systems keeps rising correspondingly. Interconnect unavoidably exist between circuit blocks. Occasionally, it could be some part of the limiting factor of total circuit speed. In this condition, a sophisticated loss compensation method targeting at interconnection loss would be quite valuable. In some other applications, where large group delay would be required, the structurewould be composed of multiple sections of energy storage element (inductors and capacitors). For a complicated structure like that, the loss would be unacceptable large. Loss compensation mechanism would be indispensable in this kind of application as well. Two chips are implemented in order to verify the correctness and practicality of the method proposed. The first one is Wideband compensated delay line with uncompensated delay line acting as control group. The second one is Versatile RF arithmetic cell single chip capable of synthesizing scalable array system. Both of the chips are fabricated in 65 -nm CMOS technology. The first chip consists of two branches of artificial transmission lines, compensation cells are inserted into one of the line between inductors and the performance without and with compensation mechanism are -8dB and -3.1dB respectively at 20GHz. With an extra power consumption of 30mW for the compensated one. The second chip is a versatile RF arithmetic cell, composed of distributed amplifiers, compensated transmission lines, and repeated variable gain stages as well as power combining stages. Two sets of the above structure are integrated into a single chip. Each branch receives different RF input signals and processes the signal according to corresponding digital control code. Various delays could be realized in each path and the final signals could be either passed to the output directly or mixed together then down-converted by a mixer. Once connecting multiple arithmetic cells together, various signal paths with different delays are now feasible. Scalable array system with arbitrary array number is readily achieved.