使用最少量緩衝器於延遲容忍系統中達成效能最佳化

Abstract

當製程進入深次微米尺寸，全局接線成為現今的系統單晶片設計中最關鍵性的難題之一。延遲容忍系統(LIS)被提出來用於解決易變的接線延遲且不需要改變原有的矽智財設計，延遲容忍系統避免掉了在產品發展過程中會浪費大量時間的延遲調整，所以延遲容忍系統是個很好的方法去加速產品設計過程。但是在不同接線上有不平衡的延遲以及後端的停止要求都會讓延遲容忍系統的效能有所衰退。我們提出了一個整數線性規劃公式去改善效能至最佳值並且使用最少量的緩衝器，我們也發展了我們的圖形表示法—量化圖。並用依據量化圖的特性，我們發展了一套降階流程去減小圖形大小但依舊維持正確性。我們也考慮了實際上晶片上會有不同的頻寬。實驗結果顯示我們的方法可以大幅降低圖形大小並且省下至少20%的緩衝器。

As manufacturing process proceeds to deep submicron (DSM) technology, global interconnect delay becomes one of the most critical obstacles in system-on-chip (SoC) design nowadays. Latency insensitive system (LIS) is a method proposed to solve variant interconnect delay without modifying pre-designed IP cores. In other words, LIS avoids modified delay iterations in product developed period. LIS offers a solution for time-to-market. However, the imbalance delay and back-pressure in LISs cause performance degradation. We propose an ILP formulation to improve performance to optimal value while maintaining minimal buffer size. We also propose a graph representation called quantitative graph (QG). Then we develop the reduction procedure on QG to decrease graph size while maintaining correctness of performance. We also consider practical situation which chip have different channel bit width on it. From the experimental results, our method reduces graph size greatly and our method saves more than 20% of buffer size than pervious works.