標題: 應用於下視網膜植入之互補式金氧半太陽能電池供電電流刺激晶片之設計
The design of CMOS solar cell powered current stimulation chips for subretinal prostheses
作者: 周敬程
Chou, Ching-Cheng
吳重雨
Wu, Chung-Yu
電子研究所
關鍵字: 下視網膜植入;視網膜晶片;電流刺激晶片;分區供電;subretinal prostheses;retinal chips;current stimulation chips;divisional power supply scheme
公開日期: 2011
摘要: 本篇論文探討應用於下視網膜植入之互補式金氧半太陽能電池供電電流刺激晶片設計,包含感光二極體架構設計、光電池電源供應器設計、控制訊號產生器設計、像素電路設計及電極設計。在標準製程下的感光二極體架構設計中,我們提出兩種垂直並聯式光電池架構,利用額外較深的二極體接面產生更大的光電流,並以台積電0.18微米CIS製程所實作的測試鍵,驗證其效率為P型基底浮接感光二極體之1.79及1.95倍。兩個用於生物體外實驗之感光二極體陣列晶片亦以相同製程實作,垂直並聯式感光二極體陣列晶片之像素為5x2,而P型基底浮接感光二極體陣列之像素則為5x5。為了提升刺激電極的表面積,我們將金球植在平面鋁電極上,並實作出單一植球及2x2植球之電極。我們以台積電0.18微米標準製程實作了一個分區供電控制測試晶片及一個植入用的分區供電感光二極體陣列晶片。分區供電感光二極體陣列晶片包含4x4像素的像素陣列,並有一感光啟動的時脈產生器,產生的參考時脈經由組合電路產生四個分區供電控制訊號,其工作頻率範圍為37.9Hz-391Hz,在1.3mW/cm2的訊號光照強度下可以得到8.55μA電流輸出,最大的單一電極輸出電荷值為26.85nC。針對體外實驗時P型基底的漏電風險,我們提出亦提出新的垂直並聯光電池整合架構並完成模擬。基於上述特性,此光電池架構、與分區供電電源控制系統對下視網膜植入的人工矽視網膜晶片設計上有相當程度的貢獻。
In this thesis, the designs of CMOS current stimulation chips including the photodiode arrays, the solar-cell power supply, the control signal generator, the pixel circuits and the stimulation electrodes for the subretinal prostheses are described. The on-chip photodiode structures named multi-junction vertically parallel (MJVP) are proposed. The MJVP photodiodes can generate larger photocurrent by additionally utilizing the deeper PN junction. A photodiode testkey is designed, fabricated and verified in the TSMC 0.18μm CMOS image sensor process. The photocurrent efficiency of the MJVP1 and MJVP2 photodiodes are 1.79 and 1.95 times as large as that in the P+/N-well photodiode with P-substrate floating, respectively. Two MPA chips are also designed and fabricated in the same process. The pixel numbers of the MPA chip with floating P-substrate and MJVP1 are 5x5 and 5x2, respectively. In order to increase the surface area of the stimulation electrodes, two different stimulation electrodes with 2x2 gold bumps and the single gold bump are simulated and fabricated. The MJVP photodiodes are also applied to the solar-cell power supply system and integrated with CMOS devices in the same process. The divisional power supply scheme (DPSS) micro-photodiode array (MPA) chip and DPSS control test chip are designed, fabricated and verified in the TSMC 0.18μm CMOS standard process. The operation frequency of the DPSS control test chip is 37.9Hz-391Hz. The DPSS MPA chip can deliver 8.55μA output stimulation current under the image irradiance of 1.3mW/cm2, and the maximum achievable charge injection of single phase is 26.85nC/electrode. The new physical integration structure of MJVP3 solar cells is also proposed to prevent the MPA chips from the P-substrate leakage in the in-vitro test. Because of its characteristic, the proposed solar cell structures and the DPSS power management system can be considered as one of the highly integrated solutions for the subretinal prostheses.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079611605
http://hdl.handle.net/11536/41731
顯示於類別:畢業論文