應用於單載波室內無線接收器之快速適應頻率域通道等化器之設計

Abstract

這篇論文針對單載波室內無線接收器提出具適應性頻率域通道等化器，系統模擬環境以及相關規格參照了IEEE 802.15.3c標準。此等化器使用了最小均平方(LMS)的適應演算法以及最小平方(LS)的通道估計來加速收斂速度同時也能保持低運算複雜度。在硬體設計方面，為了降低額外的通道估計電路的面積，在最小均平方以及最小平方上使用了硬體資源分享技術。整個基頻電路工作頻率是216MHz且8倍平行化，因此最高的資料傳輸率可達到2.9Gbps。在本論文裡以C語言以及Verilog硬體描述語言做為模擬平台，模擬的結果顯示在信雜比為10dB時，此頻率域通道等化器在未具有任何編碼保護下可達到1.54*10-4的位元錯誤率。硬體合成使用了65奈米1.2伏特1P9M CMOS製程，在不包含快速(逆)傅立葉轉換下，整體的等效邏輯閘數為50.4萬個邏輯閘，而功率消耗為81.87毫瓦。

This work proposes an adaptive frequency-domain equalizer (FDE) for Single Carrier Indoor Wireless Receiver. System simulation and specifications are based on the IEEE 802.15.3c standard. The proposed adaptive FDE uses Least-Mean-Square (LMS) algorithm with the Least-Square (LS) channel estimation to accelerate the convergence speed with low computational complexity. In the hardware design, the hardware sharing technique is used to combine the LMS and LS and reduce the overhead of the additional channel estimation hardware resource. The baseband design is eight times parallelism and is operating at 216 MHz clock rate. Thus, the maximum data rate can be up to 2.9 Gbps. The simulation models are built with C language and Verilog HDL and the simulation result shows that the proposed FDE can achieve 1.54*10-4 BER (uncoded) at 10 dB of Eb/N0. The implementation using 65 nm 1.2V 1P9M CMOS process has gate count of about 504k gates (excluding FFT and IFFT) and consumes 81.87 mW.