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dc.contributor.author辜柏翔en_US
dc.contributor.authorKu, Po-Hsiangen_US
dc.contributor.author荊鳳德en_US
dc.date.accessioned2014-12-12T01:27:20Z-
dc.date.available2014-12-12T01:27:20Z-
dc.date.issued2008en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079611628en_US
dc.identifier.urihttp://hdl.handle.net/11536/41753-
dc.description.abstract本論文展示一種以非對稱輕摻雜汲極金氧半導體電晶體來製作之2.4GHz功率放大器,它可以用TSMC 0.18μm的CMOS一般製程環境來實現。此非對稱輕摻雜汲極金氧半導體電晶體擁有的汲極源極崩潰電壓大約為一般電晶體的2倍,所以這個設計約可穩定的操作在2.5V~3V,而較高的操作電壓使得電路有優越的功率。根據模擬的結果,功率增益可以達到26.5dB,輸出功率P1dB可以達到24.9dBm,功率增加效率(PAE)在P1dB點可以達到20%,與超過40dBm的輸出三階互調截點(OIP3)。 未來的製程不斷縮小,降低工作電壓對於功率放大器是很大的設計瓶頸,此種功率單元的設計方式,將會是製程整合的良好解決方案。zh_TW
dc.description.abstractThis paper presents a 2.4 GHz CMOS power amplifier with asymmetry-LDD transistor and implements in TSMC 0.18μm CMOS technology. The asymmetry-LDD transistor has about twice drain breakdown voltage to the conventional transistor, hence the voltage source in the design can supply about 2.5V to 3V. And the power amplifier can achieved higher output power. According to simulation result, the power gain is 26.5dB, output P1dB is 24.9dBm, the PAE at P1dB is 20%, and OIP3 is over 40dBm. In the future, the low voltage is a bottleneck to power amplifier. So this power cell design might be a solution to integrate RFIC power amplifier into system on chip (SOC) with lower cost.en_US
dc.language.isoen_USen_US
dc.subject功率放大器zh_TW
dc.subjectpower amplifieren_US
dc.title非對稱輕摻雜汲極金屬氧化半導體電晶體應用於2.4GHz之功率放大器zh_TW
dc.titleA 2.4GHz CMOS Power Amplifier with Asymmetric-LDD MOS Transistorsen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis


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