Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 許婉玲 | en_US |
| dc.contributor.author | Hsu, Wan-Ling | en_US |
| dc.contributor.author | 周景揚 | en_US |
| dc.contributor.author | 黃俊達 | en_US |
| dc.contributor.author | Jou, Jing-Yang | en_US |
| dc.contributor.author | Huang, Juinn-Dar | en_US |
| dc.date.accessioned | 2014-12-12T01:27:22Z | - |
| dc.date.available | 2014-12-12T01:27:22Z | - |
| dc.date.issued | 2009 | en_US |
| dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT079611645 | en_US |
| dc.identifier.uri | http://hdl.handle.net/11536/41771 | - |
| dc.description.abstract | 進入深次微米時代,過長的連線導致過大的延遲,使得系統的效能難以繼續提高。在過去數種分散式暫存器架構已被提出,企圖使用較短的區域連線進行大部分的資料傳輸,以解決延遲的問題。在本篇論文中,我們提出一種分散式架構,稱之為考慮島間傳遞延遲的分散式暫存器檔案的架構。在這個架構上,提出一個合成流程使得整體效能盡可能達到最好。首先,分配運算子到島上得到一個初步的結果;接著,利用反覆增加效能的方法,嘗試得到更佳的結果。由實驗結果得知,與前作相比,我們可以將效能增加平均達到百分之二十九點二。 | zh_TW |
| dc.language.iso | zh_TW | en_US |
| dc.subject | 分散式架構 | zh_TW |
| dc.subject | distributed register architecture | en_US |
| dc.title | 考量島間傳遞延遲的分散式暫存器檔案架構之效能考量架構合成 | zh_TW |
| dc.title | Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay | en_US |
| dc.type | Thesis | en_US |
| dc.contributor.department | 電子研究所 | zh_TW |
| Appears in Collections: | Thesis | |
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.

