應用於三維積體電路之矽穿孔延遲測量器

Abstract

近年來，隨著半導體製程的不斷進步，電晶體大小已微縮至奈米規模。另一方面，隨著微影製程的困難度愈來愈高，造成新一代製程的製造成本急遽上升。在成本和效能為考量目的之下，工程師們試著將晶片堆疊起來，並建構SiP的概念使晶片效能提升、面積縮小。這些堆疊的晶片便是所謂的三維積體電路。其中，負責層與層之間訊號與電源連線的矽穿孔技術扮演著極為重要的角色，利用矽穿孔技術可以大幅縮短線長，提升晶片效能。 受到製程變異影響，訊號通過兩根相同TSV時會產生延遲時間差，可能造成同步電路系統準確度受到影響。在此篇論文中，我們設計了一個矽穿孔延遲測量器電路，它可以準確地計算訊號間的延遲時間差，協助後段電路調整此延遲時間差以降低訊號間的延遲誤差。 我們運用台積電90nm CMOS製程進行HSpice模擬，此電路的最大精確度約0.74ps，模擬結果顯示延遲誤差小於0.74ps，證明電路確實能精準算出延遲時間差；此外，此電路的電晶體使用個數約1200個，和一個數位電路系統動輒數百萬顆電晶體相比，成本非常小，適合嵌於三維積體電路中作為測試電路。

The manufacturing cost of the advanced process technology rises rapidly; on the other hand, the design complexity of modern designs also increases. To conquer the high cost of a large scale design, the stacked 3D IC is developed. Through-silicon-vias (TSVs) are widely used for vertical interconnection between layers in 3D ICs. Due to process variation, even when a signal passes through two different paths composed of the same series of TSVs, these two paths may incur a delay difference and affect the accuracy of a synchronous system. In this thesis, we present a TSV Delay Meter for calculating delay difference between two paths by HSpice with TSMC 90nm CMOS process. Our results show that the maximum resolution of the meter is about 0.74ps and the simulated delay errors are lower than 0.74ps as well. Hence, the TSV Delay Meter can precisely detect delay difference.