氟鈍化製程與氮氧化層於高介電常數金氧半場效應電晶體與快閃記憶體的特性研究

Abstract

許多論文都證實了氟鈍化製程可以改善元件的基本特性，如增加元件的操作電流，提升遷移率，也可以降低閘極漏電流，更進一步改善了元件在施加偏壓時的可靠度。而本論文所提出的氟鈍化製程為在元件製做完成後，再接續的PMD層時，由一般的氧化層更換成含氟離子的氧化層 (FSG) ，而含氟離子氧化層我們可以簡單的經由電漿增強式化學氣相沉積機台，在沉積氧化層的同時引入四氟化碳 (CF4) 的氣體。再經由後續金屬化製程結束後的熱製程 (Sintering) 將氟離子從PMD層驅入閘極介電層來改善元件特性。在元件完成後，經由材料分析我們也證實了，從XPS Hf4f的分析得知經過氟鈍化製程後Hf4f5/2與Hf4f7/2的Binding energy都有明顯的變大。此乃因為氟離子有效鈍化二氧化鉿高介電常數材料內的氧空缺與基板的表面缺陷，而導致較大的Binding energy，因此也提供了較強的鍵結能量 (Hf-F or Si-F)，諸如遷移率衰退、次臨界擺幅、閘極漏電流、閘極引起汲極漏電流等，皆有明顯改善。此外也經由可靠度測試分析，在正偏壓-溫度效應 (PBTI) 測試上觀察到在電壓應力破壞下，均有較小的臨界電壓的偏移、本體缺陷與界面狀態密度產生而引起的元件不穩定性，使得元件特性獲得改善及具有高度穩定性的可靠度呈現，而這些改善的原因就是來自於氟離子鈍化了高介電常數材料的本體缺陷及基板表面的缺陷狀態後產生的效果。 一般應用於N型金氧半場效應電晶體的單軸應變矽技術為在元件完成後，沉積一層具伸張應力 (tensile stress) 的氮化矽層，來改善元件的遷移率。在此我們提出於單軸應變矽元件製做前先將氟離子佈植進入矽基板，讓氟離子預先鈍化表面懸鍵而提供較強的鍵結能量 (Si-F)，來改善因沉積氮化矽層時產生過多的Si-H導致可靠度劣化的現象。元件製做完成後，不論是在固定閘極 (CVS) 或熱載子偏壓分析 (HCS) 的量測下，都可觀察到其可靠度明顯的改善。然而在基本特性，如驅動電流，並沒有如前述實驗在引進氟離子後有明顯的改善現象，可以推論為氮化矽層對元件產生應力改善驅動電流的現象遮擋了氟鈍化技術於元件上對於基本特性的改善現象。 近來許多研究以高介電常數材料來取代SONOS的氮化矽捕捉層或二氧化矽阻擋層來進一步改善元件的寫入速度與資料保存能力。在我們製作以二氧化鉿為SONOS非揮發性快閃記憶體的捕捉層 (SOHOS) 的同時，我們做了相當多的氟鈍化製程於與金氧半場效應電晶體的實驗，都證實了其改善的現象，並發現氟鈍化製程可以鈍化閘極介電層的氧空缺，所以閘極漏電流可以被大量改善，進一步經由Frenkel-Poole電流導通機制分析，氟鈍化製程可以增加的高介電常數材料內的捕捉能階，由原本的淺捕捉能階 (shallow trap)，再經由氟鈍化後變為深捕捉能階 (deep trap)。因此我們將這個現象應用於非揮發性快閃記憶體的捕捉層上，在沉積完二氧化鉿捕捉層後，再經由四氟化碳電漿處理，將原本電荷儲存在淺捕捉能階變為儲存在深捕捉能階，因為當電子儲存在深捕捉能階時，相較於儲存在淺捕捉能階時較難逃逸，所以可以進一步改善記憶體的資料保存能力，由實驗的量測的結果也驗證了我們所提出的方法，確實改善了記憶體的資料保存能力，但卻沒有影響到寫入與抹除的操作特性。 穿遂氧化層在閘極堆疊式的快閃記憶體的資料保存能力上扮演著重要的角色，因此許多論文研究探討氮氧化層 (SiON) 與乾式氧化層 (Dry oxide) 做為穿遂層時的特性與可靠度比較，而本次實驗我們先將氮氧化層製作於MOSFET，經由可靠度分析後可得到較低的介面狀態 (interface state) 與本體缺陷 (bulk defect) 漂移，進而將其運用於SOHOS非揮發性快閃記憶體元件上，並探討其SOHONS與SOHOS的寫入抹除特性，資料保存能力與元件耐久力的測試。經由量測分析結果顯示，將乾式氧化層更換為氮氧化層後對於寫入特性上有些微的改善，但元件抹除速度卻稍微的降低。進一步看到可靠度的分析時，室溫量測時的資料保存能力顯然在更換為氮氧化層後有進一步的改善，而資料保存能力在量測溫度提高至125oC時改善現象更為明顯，然而對於元件耐久力的測試，均可看到兩種元件在經過10000次的寫入抺除特性後，其記憶窗口並沒有明顯的退化，而經過10000次的寫入抹除後，元件將遭受許多的損傷，因此以氮氧化層來取代傳統乾式氧化層更可看到元件在經過10000次的寫入抹除後明顯提高了資料的保存能力，而傳統的乾式氧化層其資料保存能力更無法達到十年的要求。

There are several fluorine passivation technologies have demonstrated the improvement of device performance: for instance, operation current, mobility, decreased gate leakage current and higher device reliabilities. In our research, we proposed the fluorinated silicate glass (FSG) PMD layer to generate fluorine passivation effect, which was formed by PECVD with SiH4, N2O and CF4 gas ambient. The fluorine atoms will diffuse through gate into gate dielectric and further passivate bulk and interface defect by subsequently 400oC sintering. From material analysis, XPS data presents the increased binding energy of Hf4f5/2 and Hf4f7/2 because fluorine atoms passivated the oxygen vacancies and interface states. Fluorine passivation process shows improved performances, including higher mobility, on current degradation, lower subthreshold swing and gate induced drain leakage. After reliability measurement, the device with FSG passivation layer also shows better immunity under positive bias temperature instability (PBTI) and hot carrier stress (HCS), such as lower threshold voltage shift, bulk and interface defect density shift. SiNX contact etching stop layer (CESL) is the most simple method to generate uniaxile strain on silicon substrate to increase device mobility. We proposed channel fluorine ion implantation (CFI) to form strong bond (Si-F or Hf-F) before device fabrication. As CFI process integrated with device fabrication, it shows the improved reliability characteristics under either constant voltage stress or hot carrier stress, but the basic performance such as on current doesn’t show any obvious enhancement, which can be referred to the mobility enhancement effect of large tensile stress CESL screen out the fluorine passivation process-induced basic performance enhancement. Recently, several researches have used high-κ material to substitute charge trapping layer (Si3N4) or blocking oxide (SiO2) of SONOS nonvolatile flash memory to improve data storage or program speed capability. In our experiment, we used HfO2 (SOHOS) to replace Si3N4 trapping layer and further integrated fluorine passivation process with SOHOS nonvolatile flash memory. In our fluorine passivation experiment, we found the lower gate leakage current after fluorine passivation process, so we utilize the Frenkel-Poole current conduction mechanism to analyze the gate leakage current. From F-P analysis, we know fluorine atoms would passivate shallow trap and remain deep trap. Hence, we use CF4 plasma treatment on SOHOS HfO2 trapping layer to form deeper charge storage level. As we know, the charge store at deeper level is helpful to improve retention characteristic because it is more difficult detrapping from deeper charge storage level. The experimental results showed CF4 plasma induced deep electron trap levels indeed improved the charge storage capability, but it did not affect the program/erase speed of SOHOS nonvolatile flash memory. The quality of tunneling layer is important for retention characteristic, so there are numerous researches focus on the comparison of SiON and SiO2 tunneling layer. In our experiment, we fabricated a simple and robust oxynitride film and integrated with MOSFET and SOHOS nonvolatile flash memory. At first, we found the MOSFET with oxynitride gate dielectric showed lower interface state and bulk defect shift after constant voltage stress; therefore, we further integrated the robust oxynitride with SOHOS nonvolatile flash memory and discussed its program/erase speed, data retention and endurance characteristics between SOHONS and SOHOS. Although the SOHONS device shows a little higher program speed, the erase speed slightly decreased. The retention characteristics also improved during 25oC or 125oC measurement. Finally, the memory window of endurance measurement did not show obvious degradation of both devices after 10000 times cycle test, but the cycled retention characteristic of SOHONS gets obvious improvement.