應用於脈波振幅調變系統之高速低功率數位化類比數位轉換器與數位類比轉換器

Abstract

在現今的有線傳輸介面中，對於高速傳輸效率的需求與日俱增。脈波振幅調變（Pulse amplitude modulation，PAM）技術為一種將多筆數位資料調變為類比振幅的傳送方式，以16PAM調變方式為例，每一個電壓振幅皆代表著4筆數位資料，其相較於二位元數位傳輸方式來說，脈波振幅調變傳輸技術可在相同的頻寬限制下提升傳輸效率。本論文是以設計於高速脈波振幅調變傳輸系統的傳輸器（TX）與接收器（RX）為主題下，設計高速的類比數位轉換器與數位類比轉換器。當所要求的傳輸速率越高，則類比數位轉換器所消耗的功率就越高，所以在本論文中提出了補償頻寬的方法來實現出高頻寬且低功率的放大器，並使用數位化方式來實現整體類比數位轉換器的電路設計，以及置入內建測試電路來簡化測試設置與提升可測試性。設計規格為5GHz及16PAM傳輸方式下的類比數位轉換器與數位類比轉換器，採用的製程為UMC 90nm CMOS Logic & Mixed-Mode 1P9M Low K Process。在類比數位轉換器與數位類比轉換器的模擬結果顯示出有效位元數為3.9bit，最大差分非線性誤差與積分非線性誤差皆小於一半的最低有效位元。所消耗的功率分別為33.7mW 與18.9mW，而含內建測試電路之整體系統消耗功率為61.9mW，晶片佈局面積為0.873mm2（950μm × 919μm）。

In modern wire-line communication systems, the request for high speed data rate is growing. Pulse amplitude modulation(PAM) technique is a transmission technique which modulates digital data into analog amplitude. As an example of 16PAM, each voltage value represents four digital data. Under the same bandwidth limitation, PAM technique rises data rate as compared to binary transmission. In this thesis, our topic is to design high speed A/D converter and D/A converter for the transmitter(TX) and receiver(RX) for high speed pulse amplitude modulation systems. A bandwidth compensation method to implement wide bandwidth and low power amplifiers is proposed, it uses digitalized technique to design the A/D converter. Besides, we also design a bult-in testing circuit to improve testability. The design is a 5GHz 4bit A/D converter and a D/A converter, using UMC 90nm CMOS Logic & Mixed-Mode 1P9M Low K Process. The simulation results show that the effective number of bit is 3.9, INL and DNL are less than 0.5LSB, the power consumption of A/D converter is 33.7mW, and 18.9mW for the D/A converter. Finally, the area is 0.873mm2 (950μm × 919μm).