智能型DMA的DSP架構設計在雙核心上的應用

Abstract

雙核心處理器雖具有平行處理的能力以達到較好的運算效能，卻會受限於記憶體資料傳輸上頻寬的限制。若透過處理器做資料傳輸，將變得非常沒有效率。而一般處理器的DMA(Direct Memory Access) 雖能有效的利用記憶體頻寬用以減低處理器傳輸上的負擔，但無法提供特殊數位訊號處理功能。在現今的處理器已經開始重視 DMA對數位訊號處理的能力設計，例如智原科技的FTMCP020以及TI DSP晶片等。針對數位訊號處理的一些特殊定址及運算，是傳統的處理器或DMA將不能發揮較好的效能，因此本論文將提出智慧型直接記憶體控制器的設計。 本論文提出一個智慧型直接記憶體存取（DMA），用以輔助雙核心處理器提升運算效能及傳輸效率。智慧型DMA控制器設計以傳統DMA傳輸模式設計加上支援五種定址模式，能夠有效選取傳輸資料區塊，降低傳輸的頻寬及處理器的負擔。本論文設計特色是具有（1）擁有內建Dual-MAC運算器搭配定址模式，可支援雙通道資料記憶體向量運算，協助處理器處理大量且具有規則與繁雜的數位訊號；（2）支援周邊輸出入匯流排，使得周邊擴充更有彈性；（3）減少約75%等待資料的時間；及（4）降低組語的程式碼。 本論文設計一個智慧型DMA控制器，並整合於一個通用雙核心處理器上，經實驗結果證明能大幅提升 FFT, DCT, FIR等運算，特別是複數FFT運算。此晶片採用UMC 90nm 製程，以Cell-based方式設計，晶片面積約2.1x2.1 mm2，預估最大操作頻率在200MHz。

Although a dual-core processor has the ability of parallel processing and has a better performance, it is limited to memory bandwidth. If the processor is used as data transmission, it will become inefficiency. However, for a general-purpose processor DMA (direct memory access) is often used to improve the effective usage of memory bandwidth, but it can not offer special functions for digital signal processing. In recent years, the processor has been respected for DMA design in the ability of digital signal processing, such as Faraday’s FTDMAC020 and TI’s digital signal processors, etc. Because the traditional processor or DMA has not more efficiency at present, this thesis proposes a novel smart DMA controller design. This thesis presents the SDMA controller in order to assist a dual-core processor improving performance and transmission efficiency. The SDMA supports five addressing modes compared with the design method of traditional DMA and four transmission types to select the region of valid data and to reduce the transmission bandwidth for the processor. The SDMA design has features as follows. (1) It has a built-in dual complex-valued multiplication-and-accumulation (Dual-MAC) to processes mass and regular data computation. Moreover, two channel can access two memory banks and perform vector operations at the same time; (2) it supports the peripheral bus to expand I/O devices flexibly; (3) it can save about 75% time wasted on data transfer; and (4) the code size can be reduced. This thesis proposes the smart DMA design is integrated into the dual-core architecture to be a DSP-like processor. By experimental results, the proposed design can achieve greatly efficiency at FFT, DCT, and FIR computation, especially in complex operations. The chip has been integrated in the total area of 2.1 × 2.1 mm2 by using UMC 90nm CMOS technology and has fabricated via the National Chip Implementation Center (CIC). The maximum clock frequency is at 200MHz with a single 1.0V supply.