一個每秒一百億次取樣之六位元高速資料轉換器對

Abstract

本論文提出一組不使用time-interleaved架構且具備六位元解析度的高速資料轉換器對之電路設計，該數位類比與類比數位轉換器並使用台積電130nm CMOS Mixed-Mode RF及聯電90nm CMOS Mixed-Mode製程實現，其設計規格分別為每秒五十億次取樣率及每秒一百億次取樣率。我們使用快閃式的架構來實現超高速類比數位轉換器。透過具備主動式負回授技術的前置放大器使比較器陣列具有超寬頻、低功率的特點，並加入負電容進一步減少系統的延遲時間。同時，我們也使用平均及內插的技巧來降低放大器的偏移誤差量以及減少放大器的數量。數位類比轉換器則使用電流導向的架構，且使用操作速度較快之電流式邏輯電路設計核心的數位電路。此種電流式邏輯除了可以大幅降低高速轉換中電源的抖動量外，也適用於低電壓的操作環境，並具備非常高速的邏輯切換能力。另一方面，為了解決該高速資料轉換器測試上的困難，我們加入可測試性機制，使實驗晶片可以進行全速運作下的動態參數量測。晶片量測結果顯示以130nm實現之該資料轉換器對在全速運作的測試模式下，輸入0.5GHz的弦波訊號並以3GS/s取樣，可測得46.1 dB的訊號雜訊比以及36.4 dB的訊號雜訊失真比，對應到5.7 bits的有效位元數。在1.2V供應電源下，整個測試晶片共消耗約790 mW之功率；而以90nm實現之資料轉換器對的晶片量測結果顯示，輸入1.1GHz的弦波訊號並以10GS/s取樣，可測得29.0 dB的訊號雜訊比以及24.2 dB的訊號雜訊失真比，對應到3.7 bits的有效位元數。在1.0V供應電源下，整個測試晶片共消耗約448 mW。

This thesis presents a non-interleaved, high speed, 6-bit data converter pair design. Two test chips have been realized in TSMC 130nm CMOS Mixed-Mode RF and UMC 90nm CMOS Mixed-Mode technology, respectively. Simulation results show the 130nm one can achieve a 5GS/s sampling rate and the 90nm one can achieve a 10GS/s sampling rate. The proposed Analog-to-Digital converter (ADC) is a flash type ADC. The wide bandwidth and low power comparators were realized by active feedback pre-amplifiers (PreAmps). Furthermore, we added the differential negative capacitors to reduce the total delay of the cascade PreAmps. Averaging and interpolating skills were applied to the outputs of the PreAmps so as to reduce the offsets and the number of the amplifiers. The Digital-to-Analog converter (DAC) is a current-steering one. The digital circuits of the data converter pair are implemented with the current mode logic (CML) gates which alleviate the issue of severe power-ground bouncing compared with conventional CMOS logic implementation. In addition, the CML gates not only have less gate delays, but also are suitable for low voltage operation. To address the difficulty of conducting at-speed tests, we added the design-for-testability (DfT) circuitry. The measurement results of the 130nm test chip show that in the at-speed test mode, the data converter pair achieves an SNR of 46.1 dB and an SNDR of 36.4 dB with the 0.5GHz sinusoidal inputs at 3GS/s. It corresponds to an ENOB of 5.7 bits. The 130nm test chip including the DfT circuitry totally consumes 790 mW from a 1.2V supply. Besides, the measurement results of the 90nm test chip show that the data converter pair achieves an SNR of 29.0 dB and an SNDR of 24.2 dB with the 1.1GHz sinusoidal inputs at 10GS/s. It corresponds to an ENOB of 3.7 bits. The 90nm test chip totally consumes 448 mW from a 1.0V supply.