適用於HomePlugAV為規格的電力線通訊系統之FFT/IFFT設計

Abstract

此論文中討論到在HomePlugAV的電力線通訊系統中所使用到的384點FFT處理器的設計。將384點FFT拆解成三級radix-22演算法以及一級radix-2和radix-3混和的演算法。我們利用FFT輸入的對稱性，提出一個可以減少記憶體使用量同時也能減少成法器個數的架構。前三集所使用的是R22SDF的架構，和一般傳統的R22SDF相比，使用的記憶體大小從381N/384減少為191N/384，其中N=384；而使用的實數乘法器個數從4log4(N/6)減少為2log4(N/6)個。而最後一級radix-2和radix-3混合的架構。記憶體大小從6減為3；並且實數乘法器個數從4減為2。並且多設計了事前處理器以及事後處理器，讓所提出可以省記憶體以及省乘法器的架構能同時適用於處理FFT及IFFT。

In this thesis, we present a 384-point FFT for HomePlugAV which the FFT input have the symmetric property. The 384-point FFT is based on radix-22 algorithm in the first three stages, and radix-2 mixed with a radix-3 algorithm at last stage. We propose methods to reduce both the memory size and the number of multipliers due to the symmetry of input. In the first three stages which use the R22SDF architecture, the memory can be reduced from size of 381N/384 to 191N/384 , where N = 384; the number of real multipliers can be reduced from 4 log4(N/6) to 2 log4(N/6) , compared to traditional R22SDF scheme. In the last stage of radix-2 and radix-3, the memory can be reduced from 6 to 3; and the number of real multipliers can be reduced from 4 to 2. A pre-processor and a post-processor are also designed, so that FFT and IFFT can be processed both.can be reduced from size of 381N 384 to 191N 384 , where N = 384; the number of real multipliers can be reduced from 4 log4 N 6 to 2 log4 N 6 , compared to traditional R22SDF scheme. In the last stage of radix-2 and radix-3, the memory can be reduced from 6 to 3; and the number of real multipliers can be reduced from 4 to 2. An pre-processor and a post-processor are also designed, so that FFT and IFFT can be process both.