具有超薄高介電常數閘極介電層與應變矽鍺通道之先進深次微米金氧半場效電晶體研究

Abstract

本論文主要研究方向為：對於目前應用於先進深次微米元件之各項技術所製作之金氧半場效電晶體(MOSFET)元件，進行其特性與可靠度(reliability)的探討。為解決超薄閘極氧化層(gate oxide)的漏電流問題，將引進氮化氧化層(nitrided oxide)與具有高介電常數(high-k)之材料來取代傳統閘極氧化層；且為進一步提升元件效能，將使用應變矽鍺(strained SiGe)材料作為元件之通道層(channel)；而為了改善高介電常數材料二氧化鉿(HfO2)之薄膜特性，將使用不同之通道表面處理方法。因此，本論文將分為三大部分來進行探討：第一部份將針對具有超薄氮化閘極氧化層之n型深次微米金氧半場效電晶體，探討其劣化(hot-electron degradation)對可靠度之影響，以及其低頻跳動雜訊(flicker noise)之特性分析；第二部分針對具有經過一氧化二氮退火(N2O-annealed)之超薄氮化矽(SiN)閘極介電層與應變矽鍺通道層之p型金氧半場效電晶體，研究其電應力壓迫(stressing)劣化機制與應變矽鍺通道層厚度對元件特性的影響；第三部分則將探討不同表面處理對超薄二氧化鉿閘極介電層薄膜特性的影響。 對於多種具有超薄(等效氧化層厚度為1.6 nm)氮化閘極氧化層之0.13 um n型金氧半場效電晶體，研究其因熱電子引起電子捕捉(electron trapping)所造成之元件劣化行為，我們發現經由多種氮化技術如氮化矽/二氧化矽堆疊(Si3N4/SiO2 stack)、一氧化氮退火氮化(NO nitridation)與電漿氮化(plasma nitridation)等所形成之超薄氮化閘極介電層，將導致比傳統閘極氧化層有較嚴重的因熱電子所引起之元件劣化現象，而此熱電子劣化行為主要是因為氮加入於超薄閘極介電層中所造成之電子陷阱(electron trap)產生，而非由介面狀態(interface state)的產生所主導，此機制亦經由綜合各方面的實驗結果而獲得證實。因為將具有氮化閘極氧化層的元件於熱電子應力壓迫後，僅發現臨界電壓(threshold voltage)的正向漂移，並無發現嚴重的次臨界電壓擺幅值(subthreshold swing)變大現象，且閘極漏電流變小，由直流電流電壓(DCIV)量測所得到之Ib–Vcb特性曲線斜率亦無明顯變化，而臨界電壓對應力壓迫時間(stress time)所得之次方值(exponent, n~0.3)很小等，皆可說明元件因熱電子引起之電子捕捉即為造成元件劣化的主要原因。此外，實驗結果也顯示了於超薄氧化層中加入氮成分，將使閘極氧化層更易有熱電子劣化現象而產生嚴重的可靠度問題。而於多種氮化技術中，我們也發現電漿氮化的方式所造成的熱電子劣化效應較小，所以對於未來具有超薄氮化閘極氧化層之奈米元件的應用深具潛力。 我們亦對於傳統二氧化矽、氮化矽/二氧化矽堆疊、一氧化氮退火氮化與電漿氮化等多種超薄閘極氧化層(等效氧化層厚度為1.6 nm)之0.15 um n型金氧半場效電晶體，研究其低頻跳動雜訊特性，並發現對於所有具有經過氮化處理之閘極氧化層元件，其跳動雜訊皆明顯的增加。其主因是來自於因氮的加入使得氧化層中電子陷阱增加所造成，因為電子陷阱的增加將提高電子捕捉/逃離(trapping/detrapping)的機率，而此正是造成低頻跳動雜訊的主要機制。另外對於電漿氮化氧化層元件，發現經熱電子應力壓迫後，其跳動雜訊並無顯著的影響，原因為熱電子應力壓迫時，雖有電子陷阱產生但亦伴隨著電子捕捉的發生，因此電子陷阱產生所引起的電子捕捉/逃離現象較為不明顯。然而當氧化層發生崩潰(breakdown)時，雖然因為崩潰為氧化層中產生大量缺陷而形成電流導通路徑(conduction path)所造成，因而導致其跳動雜訊明顯增強，但氮化氧化層增強的幅度卻較傳統氧化層和緩。此外，也發現雜訊頻率指標(frequency index of the noise spectrum)將隨著閘極偏壓而改變，且亦與氧化層的電子缺陷有很密切的關係，而熱載子劣化與氧化層崩潰都將造成傳統氧化層與氮化氧化層的雜訊頻率指標變小。綜合此低頻跳動雜訊的特性來看，電漿氮化技術所製作之氮化氧化層因具有較佳的薄膜品質，使未來奈米元件在類比與高頻電路應用上亦表現了其可行性的潛力。 另一方面，我們成功地結合了應變矽鍺通道與超薄一氧化二氮退火(N2O-annealed)之氮化矽閘極介電層，製作出p型金氧半場效電晶體。此元件具有厚度為50 nm的Si0.85Ge0.15通道層，與等效氧化層厚度為3.1 nm的一氧化二氮退火之氮化矽閘極介電層，且由實驗結果顯示此元件亦有表現不錯的開/關與輸出特性。此外，透過數種不同的量測方式，我們將針對該元件的可靠度進行分析，所使用的方法有應力壓迫引發漏電流(SILC)、汲極雪崩熱載子(DAHC)注入、通道熱載子(CHC)注入以及負偏壓溫度不穩定性(NBTI)等。比較各個方法所得之分析結果後發現，對於元件的長時間劣化行為來說，因為在應力壓迫後僅發現很微小的劣化現象，因此可以確信經一氧化二氮退火之氮化矽閘極介電層具有極佳的薄膜品質。此外，我們亦發現熱載子劣化比負偏壓溫度不穩定性的劣化較為嚴重，其中又更以通道熱載子應力壓迫所造成的劣化為所有劣化行為中最劇烈的。同時我們也發現介面狀態的產生即為導致熱載子所引發劣化現象的主要機制，而對於負偏壓溫度不穩定性的劣化則主要是由電子捕捉行為所主導。 進一步地，我們發現應變矽鍺通道層的厚度對於具有應變矽鍺通道，與超薄一氧化二氮退火氮化矽閘極介電層之p型金氧半場效電晶體特性有很大的影響，若將應變矽鍺通道層厚度控制在小於15 nm以下，我們將可獲得極佳的元件特性，如次臨界電壓擺幅值為68 mV/dec 、介面狀態密度為1×1011 eV-1cm-2、較小的接面(junction)漏電流大小以及比傳統矽通道元件高過50%大小的電洞遷移率(hole mobility)等，而此結果亦表示使用經一氧化二氮退火之氮化矽薄膜作為閘極介電層將與應變矽鍺通道層之間可獲得極佳的介面品質，進而提升元件的特性與效能。 最後我們探討了不同的沈積前(pre-deposition)表面處理方法對二氧化鉿閘極介電層電性的影響，而表面處理方法有氫氟酸浸潤(HF-dipped)、氨氣退火氮化(NH3-annealed)與快速高溫氧化(RTO-treated)等三種。 由實驗結果可知，經過氨氣退火氮化表面處理後具有較佳的二氧化鉿薄膜特性，原因為其漏電流較低，且具有較小的等效氧化層厚度(EOT)，以及適度大小的遲滯寬度(hysteresis width)。相對的，快速高溫氧化處理雖然因為可獲得較厚的等效氧化層厚度而有效的降低漏電流，但卻有相當嚴重的遲滯效果。另外，我們亦針對初始反相偏壓(initial inversion bias)、溫度與量測頻率等對遲滯效果的影響，對所有經過不同表面處理方法所製作的薄膜進行研究。結果顯示，遲滯寬度將隨著量測時的初始反相偏壓增加而變大，而隨著量測溫度升高而變小，但卻不易受量測頻率的影響而有很大的改變。並且綜合我們的實驗結果，亦可發現遲滯寬度大小對於初始反相偏壓與溫度皆呈指數型關係，而此關係亦可用一個一般性的經驗式來表現，此經驗式可表示為 的形式。再者，我們發現陷阱輔助穿遂(trap-assisted tunneling)效應為所有薄膜的導通電流機制，因為其電流密度在低電壓時比起在高電壓時對溫度的改變有較劇烈的變化，而根據陷阱輔助穿遂模型，我們亦萃取了所有相關的參數並表列比較之。

We have investigared the device characteristics and the reliability of the MOSFETs fabricated by advanced deep sub-micron technologies. To reduce the intolerable leakage current of the ultra-thin gate oxide, the nitrided oxides and high-k gate dielectrics are introduced to place the conventional gate oxide; the strained SiGe layer is applied to be the device channel for enhancing the device performance; various surface treatments are performed to improve the quality of high-k HfO2 film. Hence, our studies are focused on three main topics. Firstly, we have investigated the effect of hot-carrier degradation on device reliability and the low-frequency flicker noise characteristics for the deep sub-micron nMOSFETs with ultra-thin nitrided gate oxides. Secondly, the degradation mechanism of high voltage stressing and the channel thickness effect on device characteristics for the deep sub-micron pMOSFETs with ultra-thin N2O-annealed SiN gate dielectric and strained Si0.85Ge0.15 channel have been studied. Finally, we have also investigated the effect of pre-deposition surface treatment on the electrical characteristics for the ultra-thin HfO2 gate dielectrics. We have investigated the device degradation caused by the hot-electron-induced electron trapping in various ultra-thin (EOT = 1.6 nm) nitrided gate oxides for 0.13 um nMOSFETs. It has been found that the nitrogen-incorporated gate dielectrics by a variety of popular techniques including Si3N4/SiO2 (N/O) stack, NO annealing, and plasma nitridation result in enhanced hot-electron-induced device degradations as compared to the conventional gate oxide counterpart. The exacerbated hot-electron degradations are attributed to the electron trap generation in the ultra-thin gate dielectric rather than the interface state generation as a result of nitrogen incorporation, and the mechanism has also been confirmed by several aspects: the positive shift of threshold voltage, the insignificant variation of subthreshold swing, the reduction of gate leakage current, no slope change of the Ib-Vcb curves for DCIV measurement, and a small exponent (n ~ 0.3) of □Vt versus stress time after the nitrided gate oxide devices were stressed. Moreover, the nitrogen incorporation into the ultra-thin gate oxide has been demonstrated to be more vulnerable to the hot-electron degradation as considering the long-term reliability issues, and the plasma nitridation has be shown to be the most promising technique of ultra-thin gate oxide nitridation for the sub-100nm device applications. The low-frequency flicker noise of the 0.15 um nMOSFETs with ultra-thin (EOT = 1.6 nm) thermal oxide, Si3N4/SiO2 (N/O) stack, NO oxynitride, and plasma nitrided oxide has been demonstrated. We have found that the nitrogen incorporation in the ultra-thin gate oxide will increase the flicker noise by introducing more electron traps. It is due to the fact that the low-frequency flicker noise is mainly generated by the trapping/detrapping of channel electrons with the interface states and the electron traps. However, the nitrogen incorporation can improve the device immunity against the hot-carrier degradation in the flicker noise because the hot-electron-induced electron trapping may suppress the effective electron traps for generating flicker noise. Moreover, moderate increase of noise level is obtained when the nitrided oxide is suffering breakdown comparing with the thermal oxide even though a significant amount of electron traps are created when oxide breakdown is occurred. We also found that the frequency index of the noise spectrum is varied with the gate bias and it is strong related to the oxide traps. Hot-carrier degradation and oxide breakdown may lower the frequency index for both thermal oxide and nitrided oxide devices. For considering the flicker noise characteristics, the plasma nitrided oxide has been demonstrated its potential for sub-100 nm MOSFET devices in analog and RF applications because of its higher oxide quality. The pMOSFET with 50-nm thick Si0.85Ge0.15 channel and ultra-thin (EOT = 3.1 nm) N2O-annealed SiN gate dielectric has been shown to have well-performing on/off and output characteristics. Several methodologies for the device reliability characterization, such as stress-induced leakage current (SILC), drain avalanche hot-carrier (DAHC) injection, channel hot-carrier (CHC) injection and negative-bias temperature-instability (NBTI), have been used and the results are compared. In terms of the long-term degradation, the excellent quality of the N2O-annealed SiN gate dielectric can be firmly obtained because only negligible degradations have been found after stressing no matter which technique was employed. Even so, the experimental results have been compared and we found that the HC degradation is worse than the NBTI degradation and the channel hot-carrier (CHC) stressing is the worst case for all kinds of reliability testing. Meanwhile, we have also verified that the interface state generation is the dominant mechanism responsible for the HC-induced degradation while the electron trapping dominates the device degradation for the NBTI stressing. We also have found that the thickness of SiGe channel has a great impact on the device characteristics. With controlling the SiGe layer thickness thinner than 15 nm, the device depicts a subthreshold swing of 68 mV/dec, the interface state density of 1×1011 eV-1cm-2, acceptable junction leakage, and more than 50% hole mobility improvement comparing to the Si channel device. Therefore, high quality interface between the gate dielectric and the strained SiGe channel can be achieved by using the N2O-annealed SiN gate dielectric and the device performance can be improved. Finally, we have investigated the effects that various pre-deposition surface treatments, such as HF dipping (HF-dipped), NH3 surface nitridation (NH3-annealed), and rapid thermal oxidation (RTO-treated), have on the electrical properties of HfO2 gate dielectrics. The NH3-annealed technique is far superior to the others because the dielectric subjecting to the NH3 surface nitridation possesses a tremendously reduced leakage current, the lowest equivalent oxide thickness (EOT), and a moderate hysteresis width. In contrast, the RTO-treated preparation can only effectively reduce the leakage current by its resultant increased physical thickness and displays considerably severe hysteresis. The dependence of hysteresis on the initial inversion bias (Vinv), temperature, and frequency are also investigated for all splits. The hysteresis width increases upon increasing the initial inversion bias and decreasing the temperature, but it is rather insensitive to the measuring frequency. Our experimental results indicate that the hysteresis width depends exponentially on both the initial inversion bias and the temperature, and it can be described well by a general empirical relationship with the form . In addition, the conduction currents through the dielectrics are probably dominated by trap-assisted tunneling (TAT) because the current densities display stronger temperature dependence at low voltage than they do at higher voltages. Based on the trap-assisted tunneling model, the corresponding parameters have been extracted and are presented.