一個適用於無線測試平台以控制弦波對齊演算法為基礎應用於三角積分調變器之低成本高準確度內建自我測試系統

Abstract

本論文提出一個應用於Σ-Δ調變器的低成本且高準確度之全數位內建自我測試電路，此內建自我測試電路是基於弦波對齊演算法所設計，弦波對齊演算法可在時域上計算出待測Σ-Δ調變器的偏移誤差、增益誤差、訊號對雜訊失真比、有效位元數以及動態範圍。所使用的待測類比電路是加入數位可測試性設計之二階Σ-Δ調變器，其數位可 測試性設計有助於降低內建自我測試電路的硬體成本。 由FPGA量測結果可證實，內建自我測試電路的測試頻寬約可達到18 kHz，而且只使用了9.9k的邏輯閘數，成功達到了低成本高效能的要求。在硬體實現方面，使用TSMC 0.18um cell library進行電路設計，並與待測Σ-ΔADC合併下線，實現了一顆完整的內建自我測試Σ-ΔADC晶片。 此外，經濟部科專HOY計劃提供了一個無線測試平台，藉由整合內建自我測試電路 和無線測試平台，可達成無線傳輸之內建自我測試，又更進一步節省了測試所需的時間 與成本。

This paper proposes a cost-effective and high-accuracy built-in self-test (BIST) design for Σ-Δ modulators based on the controlled sine wave fitting (CSWF) method. The CSWF method calculates the offset error, the gain error, the signal-to-noise- and-distortion ratio (SNDR), the effective number of bit (ENOB), and the dynamic range in time domain. The analog core under test is a 2nd-order design-for-digital-testability (DfDT) Σ-Δ modulator. The DfDT structure may help to simplify the hardware of the BIST design. The FPGA verification results show the test bandwidth of the BIST design is almost 18 kHz. The hardware overhead of the BIST design is as small as 9.9k gates. The BIST design is implemented by a TSMC 0.18um cell-based library. By embedding the the BIST circuitry with the Σ-Δ ADC, a fully integrated BIST ADC test chip is implemented. The Project HOY provides a wireless test platform. The wireless test platform further saves the test time and the test cost of the BIST ADC.