完整後設資料紀錄
DC 欄位語言
dc.contributor.author江志偉en_US
dc.contributor.authorChiang, Chih-Weien_US
dc.contributor.author張文鐘en_US
dc.contributor.authorChang, Wen-Thongen_US
dc.date.accessioned2014-12-12T01:27:56Z-
dc.date.available2014-12-12T01:27:56Z-
dc.date.issued2009en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079613531en_US
dc.identifier.urihttp://hdl.handle.net/11536/41969-
dc.description.abstract本論文的目標是整合多核心架構以及視訊解碼演算法,因此我們建構了一顆主核心與四顆副核心的多核心系統並在此系統架構下進行資料的平行處理,所以必須將運作於單核心的解碼程式改寫成多核心程式,而多核心程式的撰寫著重在兩大重心,找出可平行運算的解碼步驟、核心間的通訊機制與資料的傳輸。 首先從 MPEG-4 的完整解碼流程中找出可平行運算的解碼步驟,由於這些解碼步驟位於不同的副核心上,所以在副核心上是選擇管狀解碼運算而不是平行解碼運算。通訊機制方面,每個副核心有信號和信箱暫存區作為核心間的溝通管道,而暫存區均只有 32-bit 的大小,所以這些通訊機制主要是用來傳送資料的位址以及傳送工作運作時的狀態。為了在四顆副核心上達到管狀解碼運算,我們便利用這些暫存區於核心之間設計一個完整的溝通程序。資料的傳輸是透過 DMA 的方式取得資料,一旦知道資料位於記憶體的位址後,不管是主核心或副核心均可以到該位址進行資料存取,除此之外,資料傳輸會出現核心間資料覆蓋的問題,所以我們便利用多個資料暫存區來避免發生此錯誤。 實作上,主核心利用信箱詢問副核心的工作進度,由此決定是否分配工作給副核心協助解碼,由於副核心間是採用管狀解碼運算,所以主核心只需和第一顆副核心溝通而不需等待其他副核心執行結束。zh_TW
dc.description.abstractThe goal of this thesis is to combine multi-core architecture with video decoding algorithm. We present a multi-core system with one main core and four secondary cores and compute data by parallel processing on this architecture. For this purpose, we must modify the single-core decoding program into multi-core decoding program. However, multi-core programming focus on finding the parallel decoding step, communicating and data transferring between cores. First of all, we find parallel decoding steps from MPEG-4 decoding flow. These decoding steps are on the different secondary core, so we use pipeline decoding instead of parallel decoding. In communication protocol, every secondary core can use signal and mailbox register to communicate with each other. These registers only have 32-bit capability, so we use it to send address of data and status of task. For achieving pipeline decoding on four secondary cores, we design a communication procedure between each core by these registers. We transfer data through DMA command. Once we know the memory address, we can read or write data to memory no matter on the main core or secondary cores. Besides, transferring these data will introduce data overwriting between cores, so we use multiple data buffer to solve this problem. In implementation, main core use mailbox to check task status of secondary core and then decide when to assign task to secondary core. Because of pipeline decoding between each secondary core, main core only need to communicate with first secondary core and don’t have to wait for other secondary core.en_US
dc.language.isozh_TWen_US
dc.subject多核心管狀視訊解碼運算zh_TW
dc.subjectMulticore Pipeline Video Decodingen_US
dc.title多核心管狀視訊解碼運算zh_TW
dc.titleMulticore Pipeline Video Decodingen_US
dc.typeThesisen_US
dc.contributor.department電信工程研究所zh_TW
顯示於類別:畢業論文


文件中的檔案:

  1. 353101.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。