一個時脈為320MHz訊號頻寬10MHz之十二位元CMOS連續時間積分三角調變器

Abstract

使用超取樣技巧的積分三角類比數位轉換器由於具有高動態範圍以及低功率消耗的優點，它被廣泛地使用在特別應用的積體電路之上。由於先進製程技術的進步以及結合連續時間類比濾波器的技巧，連續時間積分三角類比數位轉換器的使用近幾年來越來越受到歡迎。因為使用了非取樣式的迴路濾波器，連續時間積分三角類比數位轉換器是可以同時達到高解析度以及10MHz以上的訊號頻寬需求，因此能成為一種在功率消耗以及面積使用上都更有效率的類比數位轉換器。 本論文提出一個頻寬為10MHz的寬頻連續時間積分三角調變器，並使用台積電的0.18微米製程實現。為了達到所需要的規格，所提出的調變器包含了一個三階主動式電阻電容積分器以及操作頻率為320MHz之4位元量化器。為了降低時脈抖動的敏感度，使用了不歸零式的數位類比轉換器脈衝整形來做實現。回授路徑的時間延遲被設定為半個取樣頻率週期並使用數位式微分器來補償。本論文所提出的積分三角類比數位轉換調變器在10MHz訊號頻寬的操作之下可以達到74dB以上之訊號雜訊比，功率消耗在1.8V之供應電壓之下為36mW。這樣的規格是可以被使用於生醫影像處理以及無線通訊的應用之上。

Over-sampling ΣΔ ADCs are widely used in application-specific ICs due to their high dynamic range and low power consumption. Thanks to the advance CMOS processes and continuous-time (CT) analog filter technique, the popularity of CT ΣΔ ADCs has been growing recently. Due to the non-sampling loop filter, it is feasible to build high-resolution CT ΣΔ ADCs with a bandwidth up to MHz at the same time, leading to more power- and area-efficient ADCs. In this thesis, a wide-bandwidth low-power CT ΣΔ modulator with 10 MHz signal bandwidth is implemented in TSMC 0.18 μm CMOS process. To realize such application scenario, the proposed CTSDM comprises a third-order active-RC loop filter and a 4-bit internal quantizer operating at 320 MHz clock frequency. To reduced clock jitter sensitivity, non-return-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the excess loop delay compensation is achieved by the discrete-time derivator structure. The proposed CTSDM achieves above 74 dB SNDR (12 ENOB) over a 10 MHz signal band. The power dissipation is 36 mW from a 1.8 V supply and the energy per conversion is 235 fJ from post-layout simulation. The proposed circuitry can be utilized in low-power medical imaging and modern wireless communications.