低功率和低電壓之電壓控制振盪器設計

Abstract

本篇論文的研究焦點著重於降低電壓控制振盪器其功率消耗及相位雜訊的設計。利用電流再利用的架構，可以使電壓控制振盪器在運作時的工作電流只需傳統型電壓控制振盪器運作時的一半而達到低功率消耗的目的。同時，我們提出在共振腔上並聯一組負阻電路，此方法可以有效降低功率損耗、供應電壓和相位雜訊。根據上述架構及方法，我們完成低功率、低電壓和低相位雜訊2.5和3.5GHz之電壓控制振盪器。由量測結果(TSMC 0.18-μm 1P6M CMOS 製程)，實作之IC均與模擬結果相近並達到預期之特性。此設計的提供電壓和消耗功率分別為0.93V、0.54mW和1V、1.9mW，其工作頻率於 3.5GHz和2.5GHz時，相位雜訊在距離中心頻率1 MHz分別為-116.9dBc/Hz和-125dBc/Hz。

The research described in this thesis focuses on the design of a low power consumption and phase noise LC-VCO. With the current-reused topology, the proposed LC-VCO can operate using only half amount of DC current compared with the conventional topologies to achieve low power consumption. Here, we also propose to add a negative-resistance cell shunt to the L-C tank, can effectively reduce of both the power consumption、supply voltage and phase noise. Based on proposed topology and novel method, we implement a low power、low voltage and low phase noise LC-VCO, which operates at 3.5/2.5 GHz. The proposed dual-band LC-VCO is implemented by TSMC 0.18-μm 1P6M CMOS process and the measured results are similar to simulation ones. Therefore, the performances of the proposed LC-VCO achieve anticipation. The measurement result of the VCO demonstrates a the power consumption and the supply voltage of its core is only 0.54 mW with 0.93 V and 1.9 mW with 1 V, the proposed LC-VCO operates 3.5 GHz and 2.5 GHz with phase noise of -116.9 dBc/Hz and -125 dBc/Hz, respectively, at 1 MHz offset frequency.