應用於功率管理單元且具無突波回授切換偵測電路之低功率延遲鎖定迴路式時脈產生器

Abstract

功率管理單元可以根據系統的操作狀況來動態調整系統操作頻率以及系統操作電壓以達到降低系統平均功率消耗的目的，像是Intel的speedstep技術就含有六種操作電壓/頻率組合，這類型的功率管理單元需要一個可程式化的時脈產生器來提供可變的操作頻率。 本論文提出一個可抑制變頻切換突波與大鎖定範圍的延遲鎖定迴路式時脈產生器，架構中使用了回授切換偵測器取代多組相位偵測器加電流幫浦的架構來抑制變頻切換突波，相較於使用多組相位偵測器加電流幫浦的架構可以有效地降低晶片面積，此時脈產生器的輸出頻率範圍為100MHz到1.6GHz，並且提供八階的操作頻率階級；量測結果顯示當系統操作在1.6GHz時鋒對鋒抖動量為23.316ps、功率消耗為37.8mW。 最後的版本則是將量測所發現的問題做修正並且重新設計邊緣合成器，在修正過後將系統輸出範圍提昇至1.8GHz，這些改進使得此系統更適合使用於功率管理單元。

A power management system can ensure system to operate within specification and achieve nominal power dissipation through power/speed modulation. For example, Intel Pentium M processor has speedstep technology which has six frequency/voltage modes to switching. For such power management system, we need a programmable clock generator to provide various operation frequencies. In this thesis, a glitch-free DLL-based clock generator using a feedback switching detector is proposed for a programmable power management system. The proposed circuitry utilizes feedback switching detector to eliminate undesired glitch problem which is generated by switching feedback stage of DLL. The output frequency range is from 100MHz to 1.6GHz with 8 steps for operation frequency. The power consumption is 37.8mW and P-P jitter is 23.316ps at 1.6GHz. After measurement we fix the problem found in measurement and revise edge combiner. The revise extends output frequency range to 1.8GHz. The improvements make this work more suitable for a power management system.