新型高FOM電容式耦合與交流電流偏壓技術的四相偏壓震盪器

Abstract

論文討論分為兩部分，其中各部分所提出電路之晶片製作皆由TSMC 0.18μm mixed-signal/RF CMOS 1P6M製程來實現。 第一部份介紹一個X頻段的QVCO，此QVCO採用兩個創新的技術:電容式耦合和交流電流偏壓技術。為了要產生低相位雜訊四相位訊號，我們提出使用兩組電容式耦合的震盪核心取代傳統使用主動元件耦合的震盪核心。經過這些耦合電容的純交流電流被利用於電路中，扮演偏壓電流原的角色。相比傳統使用直流固定電流源的四相位或是插動震盪器，使用交流電流偏壓可以增加振福和降低來自電晶體的相位雜訊。使用這兩種新技術的QVCO表現出高達190.5的卓越FoM數值。第一部份也分析了此QVCO的特性包含項位雜訊，振福，震盪頻率，並且將其特信與傳統四相位振盪器相比。理論上使用這兩個新技術可以達成3 dB的相位雜訊改善相比傳統的四相位振盪器。QVCO實現於TSMC 0.18μm製程可震盪在9.2~10.4GHz之間，消耗的功率為3.6mW在1.5V的電壓供應下，操作在10.4GHz時有-115.7 dBc/Hz @ 1MHz的相位雜訊。 第二部分則提出一種新型的低雜訊電容耦合方式來完成注入鎖定，產生所需的四相位輸出訊號，並且利用此大訊號弦波輸出來達成尾端電流之自我偏壓切換(Self-Switching Bias)，這種新型態的電容耦合與尾端電流自我偏壓切換震盪器可以同時達成低雜訊與低功率損耗的優點。根據量測結果顯示:本QVCO震盪頻率為4.83-5.30 GHz，在供應電壓為1.3V之條件下，功率損耗約為3.64mW，相位雜訊為 -125.8 dBc/Hz @ 1MHz，而figure-of-merit (FOM)則為-193.87 dBc/Hz。 第二部分介紹一個電流再利用的四相位振盪器（CR-QVCO）並使用前述的兩樣新技術（電容式耦合和交流電流偏壓技術）。我們將QVCO設計在5 GHz的操作頻段上並以1.3V作為供給電壓，此QVCO呈現出一個高達193.87卓越FOM，量測的相位雜訊是126 dBc/Hz ＠MHz在消耗功率為3.64 mW的情況下。為了做實際的相位雜訊比較，一個傳統使用閘極至基極耦合式的CR-QVCO也被實現於TSMC 0.18μm製程，並設計期有相同的功率消耗。量測的比較結果CR-QVCO在使用"電容式耦合和交流電流偏壓技術"下呈現相較於傳統使用"用閘極至基極耦合"T呈現一個6dB相位雜訊改善。

This thesis consists of two parts. All the proposed circuits were implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology. Part I introduces an X-band quadrature voltage-controlled oscillator (QVCO) based on two novel techniques: capacitor coupling and sinusoidal current biasing. To generate quadrature phase signals with low phase noise, the proposed design uses two capacitor-coupled LC-tank cores instead of active device –coupled cores. Sinusoidal currents through these capacitors bias the oscillator, increasing oscillation amplitude and reducing the phase noise contribution from cross-coupled transistors compared to existing QVCOs or VCOs biased with a constant current. The proposed QVCO with these two novel techniques achieved an excellent figure-of-merit (FOM) of 190.5 dBc/Hz. Part I also analyzes the properties of this QVCO, including its phase noise, oscillation frequency, and amplitude and compare proposed QVCO with conventional QVCO. Using these two techniques allow the proposed QVCO to achieve at least a theoretical 3 dB phase noise improvement compared to conventional LC-QVCOs. Implemented in a standard 0.18 um CMOS process, the proposed QVCO had a frequency tuning range of 9.2~10.4 GHz and a phase noise of -115.7 dBc/Hz @ 1MHz from a carrier of 10.4 GHz while consuming 3.6 mW with 1.5 V voltage supply. Part II present a current-reused quadrature LC-VCO (CR-QVCO) based on capacitor-coupling and sinusoidal current bias technique. The proposed CR-QVCO was designed for 5 GHz operation under supplied voltage of 1.3 V. The proposed QVCO presented an excellent FOM of 194.5. Measured phase noise was -126 dBc/Hz at 1MHz offset while power consumption 3.3 mW. For phase noise comparison, the conventional CR-QVCO based on back-gate coupling technique and the proposed QVCO both were fabricated by a 0.18-μm CMOS technology and designed to have the same power consumption. The measured comparison showed an improvement of 6dB on phase noise.