設計低相位雜訊四相位震盪器與高增益降頻混頻器

Abstract

本論文討論分為兩部分，其中所提出電路之晶片製作皆由TSMC 0.18 μm mixed-signal/RF CMOS 1P6M製程來實現。 第一部分為結合電流再利用電路並利用考畢茲電容耦合產生四相位之震盪器。此四相位震盪器存有這兩種電路的優點，且從模擬中可得到利用電容耦合產生四相位並不會產生額外的相位雜訊之結論。根據量測結果顯示:本QVCO震盪頻率為4.57~5.02 GHz，在供應電壓為1.8 V之條件下，功率損耗約為8.46 mW，相位雜訊為-119 dBc/Hz @1 MHz，而figure-of-merit (FOM)則為-183.7 dBc/Hz。 第二部分則提出低雜訊放大器運用在混頻器的射頻轉導級的高增益混頻器，這種整合型態的混頻器，利用低雜訊放大器的功能，可以同時在一個混頻器中達成高增益與低功率損耗的優點，並且減少面積使用以及避免多個電路整合到單一晶片時所遇到的匹配問題。第三章電路從分析混頻器各個區塊以達到高增益以及低雜訊，量測時，匹配的S參數14~20 GHz皆在 -10 dB以下，12~16 GHz增益頻段中有18.327 dB的最高轉換增益，而雜訊指數最小值13.2 dB，三階截斷點為 - 7.5 dB，而功率損耗為7.56 mW，FOM為191.42；第四章中除了包含第三章設計方法外，在射頻轉導級並接兩個CCC CG-LNA和CS-LNA以達到寬頻中也具有高增益與低雜訊，量測的S參數從4 GHz到20 GHz皆在 -8 dB之下。在2.7~17.8 GHz增益頻段中只有22.7 dB的最高轉換增益，而雜訊指數最小值10.45 dB，三階截斷點為 -10 dB，而功率損耗為12.058 mW，FOM為192.04。

This paper consists of two parts. All the proposed circuits were implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology. Part I presents a Colpitts current-reused QVCO based on capacitor coupling. The proposed QVCO exists the advantages of Coltpitts and current-reused circuit. Furthermore, using capacitor coupling to generate quadrature signals doesn't make extra phase noise. According to the measured results, the oscillation frequency is 4.57~5.02 GHz, and the power consumption is about 8.46 mW at the supply voltage of 1.8 V. The phase noise at 1 MHz offset is -119 dBc/Hz and the figure-of-merit (FOM) of the proposed QVCO is about -183.7 dBc/Hz. Part II proposes a high gain mixer with low noise amplifier (LNA) in the RF trans-conductance stage of mixer. Using the ability of LNA, this integrated mixer can achieve high conversion gain and low power consumption in one circuit. Furthermore, it reduces the area and avoids the problem of matching that many components integrate in SOC. In chapter 3, analyzing each block of mixer achieve high conversion gain and low noise figure. During measurement, the matching s-parameter is below -10 dB in 14~20 GHz. The measured bandwidth of conversion gain ranges from 12 to 16 GHz and the maximum gain is 18.3 dB at 14 GHz. The minimum noise figure is 13.2 dB. The measured linearity shows that IIP3 is -7.5 dB. The power consumption is 7.56 mW and the FOM is 191.42；In chapter 4, including the analytic method of chapter 3, constructing cascade construction by CCC CG-LNA and CS-LNA at the RF trans-conductance stage achieves high conversion gain and low noise figure in wide band. The measured s-parameter is below -8 dB in 4~20 GHz. The measured bandwidth of conversion gain covers from 2.7 to 17.8 GHz and the maximum gain is 22.7 dB at 4 GHz and 16 GHz. The minimum noise figure is 10.45 dB. The measured linearity shows that IIP3 is -10 dB. The power consumption is 12.058 mW and the FOM is 192.04。