低相位雜訊電流再利用震盪器 雙端平衡式低功率高增益混頻器之設計與研究

Abstract

本論文討論分為三部分，其中各部分所提出電路之晶片製作皆由TSMC 0.18μm mixed-signal/RF CMOS 1P6M製程來實現 。 第一部分為一個低相位雜訊電流再利用震盪器，由於傳統電流再利用震盪器需要一個容值非常高的外接電容用以連接源極端的電晶體(20PF up) ，我們將Cgnd串聯電感，Cgnd的容值由20PF大幅降低至1PF且可以整合在單一晶片上而無須掛一個External Capacitor。根據量測結果顯示:本VCO震盪頻率為4.78 - 5.33 GHz，在供應電壓為1.8V之條件下，功率損耗約為5.76 mW，相位雜訊為 -117.8 dBc/Hz @ 1MHz ，而figure-of-merit (FOM)則為-183.78 dBc/Hz。 第二部分為一個採用後閘極耦合 (Back-Gate Coupled)方式產生四相位輸出之電流再利用震盪器。此四相位震盪器利用雙回授機制來達成改良型自發性轉移電導匹配(Modified Spontaneous Transconductance Match, M-STM)，可有效降低NMOS與PMOS因製程變異對於轉移電導匹配上的影響，而可獲得更佳的輸出振幅平衡。根據量測結果顯示:本QVCO震盪頻率為4.84 - 5.17 GHz，在供應電壓為1.3V之條件下，功率損耗約為5.04mW，相位雜訊為 -117.4 dBc/Hz @ 1MHz，而figure-of-merit (FOM)則為-184.07 dBc/Hz。

第三部分為一個雙端平衡式低功率高增益混頻器，一般來說，主動式混頻器 (active mixer) 可以提供較高的增益，而且Gilbert–cell 混頻器相較於single–balanced 混頻器則提供較好的LO-IF isolation，但代價是必須付出較高的消耗功率以及較高的noise figure。因此本部分嘗試設計出擁有高增益但同時又擁有低消耗功率的混頻器電路。利用加入耦合電容來藉此放大看進之轉導值，達到不提高RL卻能提高增益的目標。根據模擬結果顯示: 本15GHz double-balanced mixer的conversion gain為17.0dB，相較於未加入偶合電容大約增加了4.7 dB，而noise-figure (NF) 大約是21.0 dB。在供應電壓為1.8V的條件下，功率損耗約為3.6mW.

This thesis consists of three parts. All the proposed circuits were implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology. Part I presents a low phase noise current-reused VCO (CR-VCO). Owning to the conventional current-reused VCO (CR-VCO) needs a high capacitance external capacitor (Cgnd) to connect the source terminals of the transistors (20PF up). By connecting the Cgnd with an inductance in series, the capacitance of Cgnd will not only largely decrease from 20PF to 1PF, but also it could fully integrate in a single chip without adding an external capacitor. According to the measured results, the oscillation frequency is 4.78 - 5.33GHz, and the power consumption is about 5.76mW at the supply voltage of 1.8V. The phase noise at 1MHz offset is -117.8dBc/Hz and the figure-of-merit (FOM) of the proposed VCO is about -183.78dBc/Hz. Part II presents a back-gate coupled current-reused quadrature VCO (CR-QVCO) which use double feedback mechanism to accomplish modified spontaneous transconductance match (M-STM) technique. This method is able to eliminate the transconductance difference between NMOS and PMOS transistors so that high output amplitude balance can be achieved. According to the measured results, the oscillation frequency is 4.84 - 5.17 GHz, and the power consumption is about 5.04mW at the supply voltage of 1.3V. The phase noise at 1MHz offset is -117.4dBc/Hz and the figure-of-merit (FOM) of the proposed QVCO is about -184.07dBc/Hz. Part III proposes a double-balanced mixer with low power and high gain. In general, active mixer could provide better conversion gain. Gilbert-cell mixer could provide better LO-IF isolation comparison with single-balanced mixer, but it needs to pay the cost of larger power consumption and noise figure. Therefore, we try to design a mixer topology with high gain and low power in this part. By adding coupling capacitors to increase the transconductance, it could enhance the conversion gain instead of increasing RL. According to the simulated results: The conversion gain of the 15GHz double-balanced mixer is 17.0dB, increasing about 4.7dB compared with the mixer without coupling capacitors. The noise figure (NF) is about 21.0 dB. And the power consumption is about 3.6 mW at the supply voltage of 1.8V