超大型積體電路連線的解析模型與最佳化設計

Abstract

隨著的積體電路複雜程度不斷增加，其金屬連線對電路特性的影響越來越重要. 在本論文中，我們發展了一系列完整的超大型積體電路金屬連線電容模型。這些電容模型包含三種結構 1) 平行的金屬線在一平板之上，2) 平行的金屬線在上下兩平板之間， 3) 不同金屬層之間的連線交錯所組成的三維電容結構。利用這些電容模型計算所得到的解和 Poisson 方程式的數值解及量測資料一致。 有了這些電容模型，我們接著推導一系列的延遲及串音雜訊模型。其包含了 1) 單一金屬連線，2) 雙線交聯的金屬連線，以及3)多線交聯的金屬連線系統。我們也提出了考慮電感效應的延遲模型。我們發現在較慢的操作頻率及長度較長的金屬線其電感效應並不明顯。本論文提出一種新的準則可以判別電感的重要與否。這個準則可以讓晶片設計工程師減少需要考慮模擬電感的時機進而減少晶片設計的時間。這裡所提出的模型皆用 SPICE 模擬驗證並得到良好的準確性。 根據以上的模型，這裡提出針對延遲及串音雜訊的表現進行金屬連線最佳化設計的方法。我們發現 1) 對於沒有上層金屬板的連線而言，最佳化的製程結構為薄的介電質層厚度，2) 對於上層有金屬板的連線，較厚的介電質層及較厚的金屬線可以提供比較好的設計容許範圍，以及 3)在較小的線寬及線距之下將，設計容許範圍會大幅度縮小。 在進入奈米級的製程時，不管是元件 (前段製程) 或金屬連線 (後段製程)，製程變動對其特性以及產品良率的影響將是關鍵性因素。因製程變動越來越明顯，設計的不確定因素越來越大，如動態/靜態功率消耗、延遲及串音雜訊的不確定。本文採取機率統計的方式來計算金屬連線寄生參數(如電容及電阻)，延遲及串音雜訊來取代傳統的corner-based 的方法。使用這種方法可以幫助設計工程師及製程工程師找到高良率的晶片設計及製造方法。使用機率統計的分析，我們發現 1) 較厚的介電質層厚度(H)及較厚的金屬線厚度(T)可以提供對製程變異比較好的抵抗力。2) 對於信號延遲分析， 水平間距 (pitch) (P) 和介電質層厚度有一最佳的關係(P/H=2.5)，此一最佳結構讓延遲對製程變異不敏感。 3) 對於串音雜訊而言，P/(T+H)=0.77 的結構對製程變異敏感度最大。設計或製程工程師應該避免此一結構。所以針對串音雜訊，我們建議佈局的範圍為 P < 0.77*(T+H) 或 P > 0.77*(T+H)。本文的內容相信對超大型積體電路的設計以及最佳化有很大的助益。

Increasing complexity in very large scale integration (VLSI) circuits makes metal interconnection a significant factor affecting circuit performance. The dramatically increased amount of interconnection line in chip makes the interconnect delay and crosstalk noise more dominant factors in the overall circuit speed. In this thesis, we first develop new closed-form capacitance formulas for three major structures commonly happened in VLSI, namely, 1) parallel lines in a plane, 2) parallel lines between two planes and 3) inter-layer wire crossings which are three-dimensional (3-D) nature. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson`s equation as well as measurement data. We then further derive closed-form solutions for the delay and crosstalk noise for several interconnect structures. The structures include, 1) interconnect system which has only one line, 2) interconnect system which has two parallel coupled wires and 3) interconnect system which has multiple wires coupled with each other. We also propose analytical models considering the effects of interconnect inductance. We found the effect of inductance is not significant for lower frequency operation conditions and longer line. Hence, another contribution of this thesis is that we propose criteria to help the designer to answer the question, “when does the interconnect inductance become important?”. It is helpful to reduce the efforts of performing full chip simulation with inductance. The delay and crosstalk models proposed in this thesis all agree well with SPICE simulations. Based on the models, interconnect delay and crosstalk performance is optimized over the range of process and design dimension of interest. In specified, we find 1) for wire without top wiring, the optimal dielectric thickness is relatively small, this agree with process concept nowadays 2) for lines with top wiring, larger dielectric thickness and wire thickness give better performance, and 3) the range of allowable wire thickness and dielectric thickness reduces seriously as the design pitch reduces. The variations in the process, whether device (front-end) or interconnect variations (backend), is becoming critical issue for nano-era chip designs. Along with increased process variations, the design uncertainty is increasing such as dynamic power consumption, delay and crosstalk noise. Traditional corner-based analysis provides pessimism or optimism design; hence, we propose the statistical parasitic (ex. capacitance and resistance), delay and crosstalk analysis methodology which help design or process engineer to deliver the robust chip design and enhance the product yield. In this study, we find 1) the thicker dielectric thickness (H) and metal thickness (T) provide better process variation immunity. 2) For delay analysis, horizontal pitch (P) and dielectric thickness has one optimum relationship (P/H=2.5) to achieve designs that could reduce performance impact due to variability. 3) For crosstalk analysis, P/(T+H)=0.77 is the structure most sensitive to process variation and both process and design engineer should prevent to use the structure. Hence, we recommend to use small horizontal pitch (P) so that P < 0.77*(T+H) or large pitch so that P > 0.77*(T+H) to minimize the impact due to process variation. These results are believed to be helpful in VLSI design and optimization.