Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

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DC 欄位	值	語言
dc.contributor.author	Chen, Shih-Hung	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.date.accessioned	2014-12-08T15:05:41Z	-
dc.date.available	2014-12-08T15:05:41Z	-
dc.date.issued	2007-09-01	en_US
dc.identifier.issn	0026-2714	en_US
dc.identifier.uri	http://dx.doi.org/10.1016/j.microrel.2007.07.095	en_US
dc.identifier.uri	http://hdl.handle.net/11536/4218	-
dc.description.abstract	CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-mu m CMOS technology to achieve 1-kV CDM ESD robustness. (C) 2007 Elsevier Ltd. All rights reserved.	en_US
dc.language.iso	en_US	en_US
dc.title	Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits	en_US
dc.type	Article; Proceedings Paper	en_US
dc.identifier.doi	10.1016/j.microrel.2007.07.095	en_US
dc.identifier.journal	MICROELECTRONICS RELIABILITY	en_US
dc.citation.volume	47	en_US
dc.citation.issue	9-11	en_US
dc.citation.spage	1502	en_US
dc.citation.epage	1505	en_US
dc.contributor.department	電機學院	zh_TW
dc.contributor.department	College of Electrical and Computer Engineering	en_US
dc.identifier.wosnumber	WOS:000250604600036	-
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