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dc.contributor.authorLin, SYen_US
dc.date.accessioned2014-12-08T15:01:35Z-
dc.date.available2014-12-08T15:01:35Z-
dc.date.issued1997-08-01en_US
dc.identifier.issn0005-1098en_US
dc.identifier.urihttp://hdl.handle.net/11536/422-
dc.description.abstractWe present a VLSI-array-processor architecture for the implementation of a nonlinear programming algorithm that solves discrete-time optimal control problems for nonlinear systems with control constraints. We incorporate this hardware module with a two-phase parallel computing method and develop a VLSI-array-processor architecture to implement a receding horizon controller for constrained nonlinear systems. On the basis of current VLSI technologies, the estimated computing time to obtain the receding-horizon feedback-control solution meets the realtime processing-system needs. (C) 1997 Elsevier Science Ltd.en_US
dc.language.isoen_USen_US
dc.subjectnonlinear programmingen_US
dc.subjectoptimal controlen_US
dc.subjectnonlinear systemsen_US
dc.subjectnonlinear controlen_US
dc.subjectimplementationsen_US
dc.subjectintegrated circuitsen_US
dc.titleBasic hardware module for a nonlinear programming algorithm and applicationsen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.journalAUTOMATICAen_US
dc.citation.volume33en_US
dc.citation.issue8en_US
dc.citation.spage1579en_US
dc.citation.epage1586en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:A1997XU55600015-
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