用於管道模式類比對數位轉換器的背景校準技術

Abstract

基於DSP信號處理設備的迅速增長, 促使了對於一個類比對數位轉換器具有更高的轉換率和更高的解析度的需要. 因為連續的振幅資訊的量子化需要類比模式操作, 類比對數位轉換器限制了DSP系統的貫輸量. 管道模式類比對數位轉換器被證明能夠運作在很高速, 但他們的解析度被限制於元件的不匹配, 有限的運算放大器增益,直流補償,電荷注入錯誤和元件的非 線性. 自已校準和背景校準技術已被開發用來改正這些非線形性. 數位式自已校準是一個非常有為的技術, 它可以改善基於交換電容器的管道模式類比對數位轉換器的準確性. 數位式自已校準最有吸引力的特點是附加最少的類比電路. 因而, 類比 精確度問題被變換成複雜的數位信號處理電路, 允許這種方法受益於CMOS元件的縮小技術.

數位式自已校準具有低複雜和高準確性好處, 但多數實施需要管道級的重組, 不可避免地打亂正常類比對數位轉換器的操作. 為了減少這缺點, 數個背景校準技術已被開發使類比對數位轉換器可以連續地校準他們的內部管道級來跟隨環境的變動, 同時執行正常類比對數位的轉換. 背景校準的付出是迅速地越來越少, 因為隨著縮小技術的進步, 所需的數位電路佔據越來越少的面積.

本論文提出一個15位元每秒40百萬取樣以交換電容器實現的CMOS管道模式類比對數位轉換器. 高解析度的達成是應用一個基於相似性的背景校準技術能監測重要管道級的轉移特性和連續地改正數字輸出代碼. 這個校準可以改正錯誤由於元件不匹配和有限的運算放大器增益. 這個類比對數位轉換器使用0.25微米1P5M CMOS的技術製造. 操作在每秒40百萬的採樣率時, 這個類比對數位轉換器達成最大SNDR的值是73.5 dB, 最大SFDR的值是93.3 dB. 晶片面積是3.8x 3.6 mm^2, 並且操作於2.5伏特的電力消耗是370 mW.

The rapid growth of DSP-based signal processing equipments prompted a need for a analog-to-digital converter (ADC) with higher conversion rates and higher resolutions. Since quantization of continuous amplitude information requires analog operations, ADCs often limit the throughput of DSP based systems. Pipelined ADCs have been shown to work at very high speeds but their resolution is limited by component mismatches, operational amplifier (opamp) finite gain, offsets, charge injection errors and component non-linearity. Self calibration and background calibration techniques have been developed to correct for these non-linearities. Digital self-calibration is a very promising technique to improve the accuracy of switched capacitor based pipeline ADCs. The most attractive feature of digital self-calibration is the minimum extra analog circuit involved. Thus, analog precision problems are translated into the complexity of digital signal processing circuits, allowing this approach to benefit from CMOS device scaling.

Digital self-calibration has the advantage of low complexity and high accuracy, most implementations need reconfiguration of the pipeline stages, which inevitably disrupt the normal A/D operation. To diminish this deficiency, several background calibration schemes have been developed to enable ADCs to continuously calibrate their internal pipeline stages to track environmental changes while simultaneously performing the normal A/D conversions. The cost of background calibration is decreasing rapidly because the required digital circuits occupy less and less area in scaled technologies.

This thesis presents a 15-b 40 MS/s switched-capacitor CMOS pipelined ADC. High resolution is achieved by using a correlation-based background calibration technique that can continuously monitor the transfer characteristics of the critical pipeline stages and correct the digital output codes accordingly. The calibration can correct errors associated with capacitor mismatches and finite opamp gains. The ADC was fabricated using a 0.25um 1P5M CMOS technology. Operating at a 40 MS/s sampling rate, the ADC attains a maximum signal-to-noise-plus-distortion ratio (SNDR) of 73.5 dB and a maximum spurious-free-dynamic-range (SFDR) of 93.3 dB. The chip occupies an area of 3.8x 3.6 mm^2, and the power consumption is 370 mW with a single 2.5 V supply.