N型砷化鎵/N型矽晶圓接合介面形態與電性研究

Abstract

三五族光學元件與矽基板的整合在光電積體電路的應用上吸引了不少目光，晶圓接合技術則能在高品質的接合介面之下將這些元件做整合。材料歷經高壓及高溫退火，在試片表面會形成化學鍵進而將材料緊密接合在一起。然而不同材料之間總是存在著熱膨脹係數差異，在高溫之下產生的熱應力不僅會造成試片分離還甚至會使試片破裂。 本實驗選擇N型砷化鎵與N型矽晶圓作為直接接合研究對象。首先以簡單的方式避免熱應力使試片可以在高溫退火後成功接合，之後以穿透式電子顯微鏡觀察微結構並作電流電壓特性量測。結果顯示存在於介面的非晶質區域厚度隨著退火溫度上升而變薄。而電性量測方面觀察到阻值隨著溫度的的上升而減小，在正偏壓觀察到起始電壓無改變，原因來自EL2與矽擴散的交互影響，在負偏壓觀察到崩潰電壓隨著溫度降低而減小，原因來自低溫時介面較厚的非晶質區域，提供電子漏電流的路徑而提早導通。

The integration of III–V optical devices and Silicon attract much interest for OEICs applications. Wafer bonding can provide high quality interface for combination of these materials. During high pressure and high temperature anneal, wafer bonded by producing covalent bond at interface. However, there always exist thermal expansion mismatch between different material, great thermal stress may cause sample debond even crack after annealing. In this study, direct wafer bonding was applied to combine n-Si and n-GaAs. A simple method was used to avoid thermal stress and sample successfully bonded after high temperature anneal. The interface microstructure was investigated by transmission electrical microscopy (TEM) and I-V characteristic was also measured. The thickness of amorphous layer decrease at higher annealing temperature. The I-V measurement shows the resistance decrease with annealing temperature increase. Under forward bias ,we found unchanged turn-on voltage, due to the EL2 and Si diffusion effect. Under reverse bias, we found break-down voltage decrease with annealing temperature decrease, due to at lower temperature, thicker interface amorphous region act as trap state, lead to more leakage current path.