使用簡單的化學氧化物及鎳驅入式結晶法改善金屬誘發結晶低溫多晶矽薄膜電晶體之效能及可靠度

Abstract

鎳金屬誘發非晶矽薄膜結晶的技術(MIC)已經被廣泛地使用於製作低溫多晶矽(LTPS)薄膜電晶體(TFTs)。然而，由於鎳金屬雜質殘留於鎳金屬誘發多晶矽薄膜之中，高漏電流一直是鎳金屬誘發結晶多晶矽薄膜電晶體(MIC TFTs)的一個問題。因此，本論文的主要目的為減少鎳金屬雜質的殘留量，提升鎳金屬誘發結晶多晶矽薄膜電晶體的電特性，並進一步探討鎳金屬濃度對於其它重要電性質之影響。 首先，我們將化學氧化過濾層(chemical oxide filter layer)引入鎳金屬誘發結晶技術的流程，以降低鎳金屬誘發結晶多晶矽薄膜電晶體的漏電流，此方法很簡單且不需額外昂貴的儀器。在沉積鎳金屬之前，我們只需額外將已沉積好非晶矽薄膜的試片浸泡入化學溶液的一個步驟。由實驗結果發現，化學氧化層的引入成功地降低鎳金屬誘發多晶矽薄膜中的鎳金屬含量，也顯著地改善金屬誘發結晶多晶矽薄膜電晶體的電特性。相較於傳統的金屬誘發結晶多晶矽薄膜電晶體 (MIC TFTs)，引入化學氧化物的金屬誘發結晶多晶矽薄膜電晶體(CF-MIC TFTs)呈現在最低洩漏電流下14.3倍，在開/關電流比增加17.3倍。其原因為化學氧化層可避免鎳金屬與非晶矽薄膜直接接觸，避免過量的鎳原子進入非晶矽薄膜並且使未反應的鎳金屬容易從表面除去。 除此之外，我們進一步地利用傳輸線的方法(transmission line method) 研究鎳金屬濃度對源/漏串聯電阻(S/ D series resistance)的影響。鎳金屬的影響除了在已知的漏電流之外，鎳濃度的降低可能會造成金屬誘發結晶多晶矽薄膜電晶體的源/漏接觸電阻隨之變化，進而影響了元件的效能（驅動能力）。因此，我們獲得一個新發現—鎳金屬濃度和元件電阻之間的相互關係。由結果顯示，源/漏接觸電阻和通道電阻皆隨著金屬誘發結晶多晶矽薄膜之中的鎳金屬濃度減少而降低。近年來，關於主動式有機發光顯示器(AMOLED)的應用，電偏壓的可靠度(bias reliability)和熱穩定性(thermal stability)已成為主要關注的課題，尤其是當元件操作於熱載子(Hot carrier)狀態及高溫環境中。本研究中也探討了鎳金屬濃度對於電偏壓可靠度及熱穩定性的影響。結果發現，低鎳金屬殘留量的元件對於熱載子應力(hot carrier stress)和升溫操作下呈現較高的抵抗能力。以上現象證明，除了已知的漏電流，減少金屬誘發結晶多晶矽薄膜之中的鎳金屬濃度亦有利於源/漏接觸電阻，電偏壓可靠度和熱穩定性。 最後，我們提出了一個新的製作多晶矽薄膜電晶體的方法，驅入式鎳金屬誘發結晶(DIC)，主要是利用氟離子佈植的方式驅使鎳金屬進入非晶矽薄膜而進行後續的金屬誘發結晶。結果發現，此方法可以有效地減少鎳金屬濃度並且鈍化(passivate)二氧化矽與多晶矽界面附近的捕捉態(trap-state)，因而使得元件的電特性(尤其是漏電流)和熱穩定性都獲得相當地改善。然而，在開啟電流(on-state current)的部份無法獲得明顯的改善，其原因可能是由於離子佈植過程中造成的通道損害或缺陷產生所致。因此，我們將暫時的氧化層引入驅入式鎳金屬誘發結晶的製程中(DICC)，主要來降低由離子佈植過程中所造成的傷害，而獲得更進一步的改善。相較於傳統的金屬誘發結晶多晶矽薄膜電晶體，此方法製備的薄膜電晶體呈現在開/關電流比(Ion/Ioff)增加9.7倍，在最低洩漏電流(Imin)則由4.06 pA/μm下降至19.20 pA/μm，另外也呈現較好的可靠度。

Ni-metal-induced crystallization (MIC) of amorphous Si (α-Si) has been widely employed to fabricate low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs). However, the high leakage current is an issue of MIC TFTs because Ni impurities trapped inside the MIC poly-Si films. Therefore, the main purposes of this thesis are to reduce Ni residues, to improve electrical performance of MIC TFTs, and further to investigate the effects of Ni concentration on others of importantly electrical characteristics. First, a chemical oxide filter layer was introduced into MIC processes to reduce the leakage current of MIC TFTs, which was simple and without extra expensive instrument. It just added a step of dipping α-Si coated sample into chemical solution before depositing the Ni film. It was found that Ni concentration was decreased successfully in MIC poly-Si films and the electrical performance of MIC TFTs with chemical oxide layer was significantly improved. Compared with conventional MIC TFTs, CF-MIC TFTs shows a 14.3-fold decrease in the minimum leakage current and a 17.3-fold increase in the on/off current ratio. This is because the chemical oxide layer can avoid Ni directly contact with α-Si, avoid excess of Ni atoms into α-Si layer and remove unreacted Ni easily from surface. Furthermore, the Ni concentration effect on source/drain (S/D) series resistance was investigated by transmission line method. In addition to well known Ni effects on leakage current, however, the S/D series resistance of MIC TFTs might be changed with reduction of Ni concentration, which also influences the device performance (driving ability). Therefore, we attained a new finding for the relation between Ni concentration and resistance. As the results, the S/D series resistance and channel resistance were decreased with the reduction of Ni concentration in MIC poly-Si. Recently, the bias reliability and thermal stability became major concerns for AMOLED display applications especially when devices are operated under hot carrier condition and high temperature environment. In this study, the effect of Ni concentration on bias reliability and thermal stability were also investigated. It was found that the low Ni residues device presented high immunity against the hot-carrier stress and elevated temperature. These findings proved that reducing Ni concentration in MIC films was also beneficial for S/D series resistance, bias reliability and thermal stability. Finally, a new manufacturing method for poly-Si TFTs using drive-in Ni induced crystallization (DIC) was proposed. In DIC, F+ implantation was used to drive Ni in the α-Si layer. It was found that the electrical performance (especially leakage current) and thermal stability of DIC TFTs were improved due to the reduction of Ni concentration and passivation of trap states near the SiO2/poly-Si interface. However, the on-state currents were nearly unchanged due to the channel damages/defects caused by ion implantation. Therefore, a cap oxide layer was introduced into DIC process (DICC) to reduce ion implant damages. Compared with that of MIC TFTs, the on/off current ratio (Ion/Ioff) of DICC TFTs was increased by a factor of 9.7 from 9.21×104 to 8.94×105. The minimum leakage current (Imin) of DICC TFTs was 4.06 pA/μm, which was much lower than that of the MIC TFTs (19.20 pA/μm). DICC TFTs also possess high immunity against the hot-carrier stress and thereby exhibit good reliability.