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dc.contributor.author葉啟瑞en_US
dc.contributor.authorYeh, Chi-Rueien_US
dc.contributor.author趙天生en_US
dc.contributor.authorChao, Tien-Shengen_US
dc.date.accessioned2014-12-12T01:29:51Z-
dc.date.available2014-12-12T01:29:51Z-
dc.date.issued2008en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079621501en_US
dc.identifier.urihttp://hdl.handle.net/11536/42412-
dc.description.abstract在本論文中,我們製造了具有高性能之P型通道的高介電常數閘極絕緣層的低溫薄膜電晶體並且探討其元件特性。為了能夠提升低溫薄膜電晶體的電性,我們採用二氧化鉿(HfO2)作為閘極絕緣層以及引進新穎的結晶技術─金屬誘發側向結晶法(MILC)─來製作高性能之元件。高載子遷移率約215 cm2/V-s、優異次臨界斜率約107 mV/decade以及低臨界電壓約-0.75 V可被得到而不需要任何的缺陷鈍化處理。 我們使用傳統直流(DC)電性量測技術來有系統地研究關於閘極負偏壓高溫應力(NBTI)劣化機制,分別對於使用固相結晶法(SPC)與金屬誘發側向結晶法(MILC)之二氧化鉿(HfO2)的低溫薄膜電晶體。在本實驗中,我們使用先前在傳統二氧化矽(SiO2)上的閘極負偏壓高溫應力之經驗公式去分析高介電常數閘極絕緣層的劣化機制。在閘極負偏壓高溫應力劣化下,實驗結果顯示閘極負偏壓高溫應力(NBTI)的劣化主要是由於表面缺陷所造成,以及使用金屬誘發側向結晶法(MILC)比起使用固相結晶法(SPC)的元件在可靠度方面有著更加穩定的性質。 最後,汲極效應在閘極負偏壓高溫應力劣化機制下亦被探討。結果顯示汲極偏壓可以降低跨在閘極絕緣層的垂直電場,並且改善閘極負偏壓高溫應力所引起的元件劣化。從實驗資料中,我們建立了汲極效應在閘極負偏壓高溫應力劣化的理論模型。此模型與臨界電壓飄移(ΔVTH)有良好的吻合因此能夠証實我們的理論。zh_TW
dc.description.abstractIn this dissertation, high performance p-channel low temperature poly-silicon thin-film transistors (LTPS-TFTs) with high-κ gate dielectrics are fabricated and investigated. In order to enhance the characteristics of LTPS-TFTs, we adopted the employment of HfO2 gate dielectric and the novel crystallization methods, metal-induced laterally crystallization (MILC), to fabricate high performance devices. High filed effect mobility μFE ~ 215 cm2/V-s, ultra-low subthreshold swing S.S. ~ 107 mV/decade, and low threshold voltage VTH ~ -0.75 V are derived from MILC-TFT with HfO2 gate dielectric without any defect passivation methods. Negative bias temperature instability (NBTI) degradation mechanism in solid-phase crystallization (SPC) and MILC LTPS-TFTs with HfO2 gate dielectric has been studied systematically with a conventional DC measurement technique. We used the previously empirical formula for traditional NBTI in SiO2 to analyze the high-κ gate dielectric in our experiment. The results showed that NBTI degradation is more dominated by the generation of interface trap states (NIT) and the MILC transistors have more stability characteristic than SPC during the NBTI stress. Finally, the drain bias effects on NBTI degradation mechanism is also investigated. The results showed that drain bias can reduced the vertical electric field across gate dielectric and improved the NBTI-induced degradation. From experimental data, the NBTI model with drain bias effect is established. A good fit on the threshold voltage shift (ΔVTH) prediction is obtained and confirms our theory.en_US
dc.language.isozh_TWen_US
dc.subject薄膜電晶體zh_TW
dc.subject高介電材料zh_TW
dc.subject閘極負偏壓高溫應力zh_TW
dc.subject金屬誘發側向結晶zh_TW
dc.subject可靠度zh_TW
dc.subjectTFTen_US
dc.subjecthigh-ken_US
dc.subjectNBTIen_US
dc.subjectMILCen_US
dc.subjectreliabilityen_US
dc.title具高介電常數閘極絕緣層之低溫多晶矽薄膜電晶體可靠度研究zh_TW
dc.titleInvestigation on Reliability of LTPS-TFTs With High-k Gate Dielectricsen_US
dc.typeThesisen_US
dc.contributor.department電子物理系所zh_TW
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