具新穎應力記憶技術之金氧半場效電晶體

Abstract

在這個研究中我們提出一項新穎的應力記憶技術-“應力無鄰近記憶技術”(Strain Proximity Free Technique)來提升元件的效能。為了克服高密度應變矽技術中因為元件微縮導致過窄多晶矽間距使得應力難以傳導至通道中的問題，所以在此情況下應力的產生應該要在閘極未定義之前就被執行。應力無鄰近記憶技術的製程不像傳統的應力記憶製程一樣，而是在閘極未定義和源極/汲極的延伸區離子佈植(Source/Drain extension)形成之前，就先使用一個拋棄式的氮化矽覆蓋層以及極快速熱退火(spike anneal)來造成。在氮化矽層移除之後，我們可以發現應力的效果可以藉由多晶矽閘極的再結晶來增強且記憶在通道中。藉由這項技術可以提升n型金氧半場效電晶體的驅動電流達到17個百分比。此外結合多晶矽閘極非晶化離子佈植製程(Poly-Gate Amorphous Implantation)，可以使飽和電流值獲得加乘性的提昇。我們也研究了這項技術中不同的極快速熱退火溫度和多晶矽厚度製程的電性以及可靠度特性。實驗結果發現較高溫度(1100oC)以及兩次的極快速熱退火(Double Spike)可以對效能還有熱載子可靠度有所提升。當最佳化這些參數之n型金氧半場效電晶體的驅動電流可以達到48個百分比的改善，並且擁有好的熱載子 (hot-carrier stress)抵抗能力。這項應力無鄰近記憶技術在未來的應變矽元件中將會成為局部應變製程中一個相當有潛力的方法。

A novel stress memorization technique- Strain Proximity Free Technique (SPFT) to improve device’s performance is proposed in this study. To overcome the scaling down issue of strain-Si that stress difficultly transmit to channel due to narrowing poly-pitch in high density devices, generation of strain should be carried out before gate patterning. In SPFT process, unlike traditional Stress Memorization Technique (SMT), a disposable nitride capping layer and subsequently spike-anneal are used before gate pattening and source/drain extension implatation. The stress effect was memorized and found to enhance the stress of channel underneath the re-crystallized poly-Si gate after the removal of nitride layer. Up to 17% enhancement on driving current of nMOSFETs is achieved by this technique. In addition, combining the Poly-gate Amorphous Implantation (PAI) process, additive enhancement of Id,sat can be obtained. Various temperatures of post-spike anneal and thicknesses of poly-silicon are both investigated on electrical and reliability characteristics. It was found that higher temperature (1100oC) and double spike annealing can further improve the performance enhancement and hot-carrier reliability. Very significant higher drive current, maximum to 48% improvement on nMOSFETs, can be attained. With the optimum of process condition of SPFT, devices show a strong resistance for hot-carrier, the SPFT scheme seen to be a promising local strain approach for future strain-Si device.