具新應力記憶技術之金氧半場效電晶體TCAD模擬綜合研究

Abstract

在本論文中我們針對一項新的應力記憶技術–“應力無鄰近記憶技術”(Stress Proximity Free Technique)提升金氧半場效電晶體的效能進行電性模擬與原理解析之研究。 傳統的製程方法無法使元件隨著載子通道微縮時藉由應變矽技術提供更高的效能提升。而開發應力無鄰近記憶技術(SPFT)在過去的研究中[0.1]已經被證實能克服在高密度應變矽技術下因元件微縮所導致的多晶矽間距過窄而造成應力難以傳導至載子通道的問題。 藉由Technology CAD模擬軟體的輔助，讓我們得以進一步瞭解在應力無鄰近技術中所使用的拋棄式氮化矽覆蓋層、極快速熱退火(Spike Anneal)、多晶矽閘極再結晶、以及接觸蝕刻停止層(Contact Etch Stop Layer)等製成步驟對元件造成的矽能隙縮窄(Bandgap Narrowing)，以及變溫量測之載子與晶格聲子散射(Phonon Scattering)、雜質-載子散射(Impurity Scattering)等物理現象。我們也藉由Technology CAD中製成模擬(Sentaurus Process)的功能分析在不同製程步驟下對元件的應力(Stress)表現與在不同量測溫度下對元件的電場(Electric Field)以及載子遷移速率(Carrier mobility)等物理特性之變化對元件電性表現的影響。

In this thesis, we focus on a novel stress memorization technique – “Stress Proximity Free Technique”, which is used to enhance MOSFETs performance, and analyze the electrical characteristics with comprehensive study from fundamental principle to advanced semiconductor theory. The conventional manufacturing techniques cannot keep improving the performance of MOSFETs with strained Si during the channel length scaling. In the past researches [0.1], it had been confirmed that SPFT can overcome the issues that poly-gate spacing became too narrow to transfer the stresses into the channel region when the channel length kept scaling down with high density strained Si technology. But there still has several factors unknown behind the SPFT process, especially for the mobility degradation during high temperature measurements. Thanks to Technology CAD, we can understand the effects of the SPFT by process simulation including disposable nitride cap, poly-gate re-crystallization, and contact etch stop layer. These will cause the silicon band gap narrowing, deformation, and phonon scattering, etc. And it also changed the electrical characteristics during elevated temperature measurements. We analyzed each process step and understood the relationship between stress effects and carrier mobility by the aid of the simulators.