應用於低暗電流和高光譜反應之互補式金氧半影像感測器分析與設計

Abstract

本論文提出、分析並設計應用於互補式金氧半(CMOS)主動式像素影像感測器(Active Pixel Sensor imager)之新型光二極體架構和應用於低暗電流和大陣列數目影像感測器之新型互補式金氧半像素架構。論文中主要包含下列三個主要部份：(1)應用於互補式金氧半主動式像素影像感測器之新型光二極體架構設計、最佳化與成果分析；(2)應用於低暗電流與大陣列數目靜態影像感測器之新型互補式金氧半像素架構；(3) 應用於低暗電流與大陣列數目影像感測器之互補式金氧半虛擬主動式像素感測器(Pseudo Active Pixel Sensor)的最佳化設計。 首先，由於暗電流在互補式金氧半影像感測器的主動式像素感測單元中主要產生於經過局部氧化矽(LOCOS)過程後的鳥嘴區和高掺雜濃度沉積引起的表面損害。此外，淺和深的pn接面分別可以改善短波長光和長波長光的光感應度。為了減少暗電流和增加整體的光譜反應，吾人提出並分析利用p型基體和輕微掺雜濃度的感測器佈植SN□當pn接面光二極體與其鳥嘴區分別被SN□和p-field 佈植包圍住的兩種新型光二極體架構。在5 □m x 5 □m的主動式像素感測單元中，採用了提出的光二極體架構並經過0.35 □m 1P3M N-well互補式金氧半技術的製造。從量測結果顯示，在5 □m x 5 □m主動式像素感測單元中，兩種吾人提出的光二極體架構與傳統架構及別的光二極體架構比較下，在2 V反相偏壓時有30.6 mV/sec和35.2 mV/sec的較低暗電流和較高的光譜反應。 其次，根據傳統的主動式像素感應器的像素架構，吾人提出一稱之為『虛擬主動式像素感應器』(Pseudo Active Pixel Sensor)的新型像素架構並應用於靜態互補式金氧半影像感測器中。這個新型的像素架構和傳統被動式像素影像感測器(Passive Pixel Sensor imager)及主動式像素影像感測器相比，具有低漏電流、高訊號雜訊比例和高填充係數等優點。一種稱之為『行零偏壓緩衝直接注入式』(Zero-bias Column Buffer-Direct-Injection)的讀出電路架構也被提出，此種讀出電路偏壓光二極體和位於行匯流排的雜散pn接面於0 V或接近0 V來減少光二極體的暗電流和列開關的漏電流。改良式的雙重三角取樣(Double Delta Sampling)電路也被使用來減少固定樣式雜訊(fixed pattern noise)、時脈回饋雜訊和通道電荷注入。352 x 288(CIF)格式的互補式金氧半虛擬主動式像素影像感測器實驗晶片是經由0.25 □m 1P5M N-well互補式金氧半技術製造。像素的大小是5.8 □m x 5.8 □m。像素讀出速率從100 kHz到10 MHz，相當於最大的畫面速率(frame rate)超過30 frames/sec。這個提出的靜態互補式金氧半影像感測器還具有58%的填充係數、3110 □m x 2760 □m的晶片面積和操作在3.3 V電源供應時產生的24 mW功率消耗。這個實驗性的晶片已經成功地證明了新提出的虛擬主動式像素感測器架構並且可以應用在低暗電流和高解析度的大陣列數目靜態互補式金氧半影像感測器系統設計。 最後，根據吾人提出的虛擬主動式像素感測器的像素架構，一應用於互補式金氧半影像感測器的像素架構稱為『最佳化虛擬主動式像素感測器』(Optimal Pseudo Active Pixel Sensor)亦被提出、分析和設計。在像素中被共享的零偏壓緩衝器可保持光二極體和位於像素匯流排的雜散pn接面偏壓於0 V或接近0 V來減少光二極體的暗電流和像素開關的漏電流。每單位像素面積的光電流與暗電流比例(PDRPA)這個係數可以定義用來描述最佳化虛擬主動式像素感測器的性能特徵。當零偏壓緩衝器被四個像素共用時被發現具有最大的PDRPA。此外、行取樣電路和輸出相關雙重取樣電路也被用來減少固定樣式雜訊、時脈回饋雜訊和通道電荷注入。352 x 288(CIF)格式的互補式金氧半最佳化虛擬主動式像素影像感測器實驗晶片是經由0.25 □m 1P5M N-well互補式金氧半技術設計和製造。在這個製造的互補式金氧半影像感測器當中，每四個像素共用一個零偏壓緩衝器下的PDRPA值等於37.7 □m-2。它也具有8.2 □m x 8.2 □m的像素大小、42%的填充係數和3630 □m x 3390 □m的晶片面積。量測到的最大畫面速率是30 frames/sec、暗電流為82 pA/cm2。量測到的光動態範圍是65dB。與主動式像素感測器架構和傳統的被動式像素感測器架構相比較時，吾人所提出的最佳化虛擬主動式像素感測器架構具有較小的暗電流、較高的填充係數和較高的光動態範圍。 根據以上的結果，我們深信吾人所提出新型光二極體架構可以被應用在具有小像素面積、高解析度和高品質的互補式金氧半影像感測系統中。此外，具有小像素面積、高填充係數和低暗電流等優點特徵之吾人所提出的新型互補式金氧半虛擬主動式像素影像感測器架構，將可以被應用在大陣列數目靜態互補式金氧半影像感測器設計中。吾人所提出之互補式金氧半最佳化虛擬主動式像素影像感測器和虛擬主動式像素感測器、主動式像素感測器、被動式像素感測器等互補式金氧半影像感測器相比較下有較低的暗電流，同時也比互補式金氧半主動式像素影像感測器有較高的填充係數。因此，吾人所提出之最佳化虛擬主動式像素感測器架構應用在高品質的互補式金氧半影像感測器時會具有較高的潛力。

In this thesis, new photodiode structures for CMOS active pixel sensor (APS) imagers and new CMOS pixel structures for low-dark-current and large-array-size imager applications are proposed, analyzed, and designed. The main parts of this thesis include: (1) design, optimization, and performance analysis of new photodiode structures for CMOS APS imager applications; (2) a new CMOS pixel structure for low-dark-current and large-array-size still imager applications; (3) optimal design of CMOS pseudo active pixel sensor (PAPS) structure for low-dark-current and large-array-size imager applications. Firstly, it is known that the dark current in the APS cell of a CMOS imager is mainly generated in the regions of bird’s beak after the LOCOS (local oxidation of silicon) process as well as the surface damage caused by the implantation of high doping concentration. Furthermore, shallow and deep pn junctions can improve the photo-sensitivity for light of short and long wavelengths, respectively. Two new photodiode structures using p-substrate and lightly-doped sensor implant SN□ as pn junction photodiode with the regions of bird’s beak embraced by SN□ and p-field implant, respectively, are proposed and analyzed to reduce dark current and enhance the overall spectral response. 5 □m x 5 □m APS cells fabricated in a 0.35 □m single-poly-triple-metal (1P3M) N-well CMOS process are designed by using the proposed photodiode structures. As shown from the experimental results, the two proposed photodiode structures of 5 □m x 5 □m APS cells have lower dark currents of 30.6 mV/sec and 35.2 mV/sec at the reverse-biased voltage of 2 V and higher spectral response, as compared to the conventional structure and other photodiode structures. Secondly, based on the conventional APS pixel structure, a new pixel structure for still CMOS imager application called the pseudo active pixel sensor (PAPS) is proposed and analyzed. It has the advantages of low dark current, high signal-to-noise ratio (SNR), and high fill factor over the conventional passive pixel sensor (PPS) imager or APS imager. The readout circuit called the zero-bias column buffer-direct-injection (ZCBDI) structure is also proposed to suppress both dark current of photodiode and leakage current of row switches by keeping both biases of photodiode and parasitic pn junction in the column bus at or near zero voltage. The improved double delta sampling (DDS) circuits are also used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed PAPS CMOS imager with the format of 352 x 288 (CIF) has been fabricated by using 0.25 □m single-poly-five-level-metal (1P5M) N-well CMOS process. The pixel size is 5.8 □m x 5.8 □m. The pixel readout speed is from 100 kHz to 10 MHz, corresponding to the maximum frame rate above 30 frames/sec. The proposed still CMOS imager has a fill factor of 58%, chip size of 3110 □m x 2760 □m, and power dissipation of 24 mW under the power supply of 3.3 V. The experimental chip has successfully demonstrated the function of the proposed new PAPS structure. It can be applied in the design of large-array-size still CMOS imager systems with low dark current and high resolution. Finally, based on the proposed PAPS pixel structure, a pixel structure called the optimal pseudo active pixel sensor (OPAPS) is proposed, analyzed, and designed for the applications of CMOS imagers. The shared zero-biased-buffer in the pixel is used to suppress both dark current of photodiode and leakage current of pixel switches by keeping both biases of photodiode and parasitic pn junctions in the pixel bus at zero voltage or near zero voltage. The factor of photocurrent-to-dark-current ratio per pixel area (PDRPA) is defined to characterize the performance of the OPAPS structure. It is found that a zero-biased-buffer shared by four pixels can achieve the highest PDRPA. In addition, the column sampling circuits and output correlated double sampling (CDS) circuits are also used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed OPAPS CMOS imager with the format of 352 x 288 (CIF) has been designed and fabricated by using 0.25 □m single-poly-five-level-metal (1P5M) N-well CMOS process. In the fabricated CMOS imager, one shared zero-biased-buffer is used for four pixels where the PDRPA is equal to 37.7 □m-2. The fabricated OPAPS CMOS imager has a pixel size of 8.2 □m x 8.2 □m, fill factor of 42%, and chip size of 3630 □m x 3390 □m. The measured maximum frame rate is 30 frames/sec and the dark current is 82 pA/cm2. The measured optical dynamic range is 65dB. It is found that the proposed OPAPS structure has lower dark current, higher fill factor, and higher optical dynamic range as compared with the APS structure and the conventional PPS structure. From the above results, it is believed that the proposed new photodiode structures can be applied to CMOS imager systems with small pixel size, high resolution, and high quality. Moreover, with the advantageous characteristics of small pixel area, high fill factor, and low dark current, it is expected that the proposed new PAPS CMOS imager structure can be applied to the design of large-array-size still CMOS imagers. The proposed OPAPS CMOS imager has the smaller dark current than those of PAPS, APS, and PPS CMOS imagers and higher fill factor than that of APS CMOS imager. Thus the proposed OPAPS structure has high potential for the applications of high-quality CMOS imagers.