高速高容量固態硬碟機之控制晶片設計研究

Abstract

本論文主要針對固態硬碟機在使用高密度NAND型快閃記憶體時，因NAND型快閃記憶體的製程高度微縮與多層次(Multi-Level Cell)記憶技術所造成的性能劣化現象，而所必需要的控制晶片設計，提出了設計方法與電路架構。尤其是特別針對在高速高容量的固態硬碟機的控制晶片設計而言。近期，由於NAND型快閃記憶體密度的快速提昇以及成本的下降，使得使用NAND型快閃記憶體的固態硬碟機來取代傳統的硬式磁碟機，以作為可攜式裝置的資料存儲設備成為極佳的選擇。然而，如果欠缺了一個有效的控制晶片來處理這些高容量快閃記憶體的性能劣化問題，以及將整體系統的性能提昇，則此固態硬碟機將會有使用上的限制，或者甚至有可能變成為無法使用的裝置。在本論文中，針對了先進NAND快閃記憶體因為密度提高與MLC (Multi-Level Cell)技術所造成的資料讀寫與區塊抹除的干擾因素增加，因而導致位元讀寫錯誤率的升高，提出了使用Systolic Array方法來構建 t-EC w-位元 並列式BCH (Bose-Chaudhuri-Hocquengham) ECC (Error-Correction Code)的硬體電路，來彌補這些性能劣化的現象，降低其位元讀寫錯誤率至一個可靠的水平。針對使用混合式多通道的快閃記憶體所構成的高速高容量固態硬碟機，提出了多模BCH ECC的電路架構，以提供一個高效率、低成本及低功率消耗的ECC電路架構。而對於對單一快閃記憶體晶片所能提供的資料讀寫速率極度有限，提出了高效能的資料傳輸硬體電路架構，以使主機系統與快閃記憶體陣列之間的資料傳輸效能達到系統所能提供的最高的頻寬利用率。針對固態硬碟機裡所存儲的資料保全機制，提出了具硬體加速器方式的CPRM (Content Protection for Recordable Media)功能實施，以得到一個高效能且低成本的資料保全架構。在本論文中，我們提出混合式的多通道非揮發性固態記憶體所組成的固態硬碟機架構及其控制晶片設計，則具有能綜合各種非揮發性記憶體之間的特性，而能達到整體固態硬碟機的最佳的成本與性能。這些非揮發性的固態記憶體中，除了NAND快閃記憶體之外，其他有如：FeRAM (Ferroelectric RAM), MRAM (Magneto-resistive RAM), PRAM (Phase-changed RAM)等。整體言之，本論文針對高速高容量固態硬碟機的控制晶片設計，提出了具體的電路設計方法與控制晶片的電路架構，使得一個合於產品規格的低成本、高資料傳輸率、高品質、壽命長的高速高容量固態硬碟機能具體的實施出來。並且，經由實際的晶片實作與測試，驗證了這些方法與電路架構的有效性與優越的性能。

In this thesis, we present the key architectures of the controller chip design for solid-state drive. The key architectures of the controller chip were developed to cover the deficiencies of NAND Flash memory and to enhance the system performance, especially for the high-speed and high-capacity solid-state drive. Nowadays, the continuous price drop of NAND flash memory makes the solid-state drives affordable and a promising candidate to replace the hard disk drives in portables. However, the solid-state drives may become inefficient or even useless without the help of an intelligent controller chip, not to mention the fulfillment of high-speed and high-capacity. In this thesis, both innovative controller designs and circuit architectures were presented for solid-state drives to overcome the NAND flash device degradation caused by technology shrinking and thus improve the system performance of solid-state drives. A t-EC w-bit parallel BCH (Bose-Chaudhuri-Hocquengham) ECC (Error-Correction-Code) construction was first proposed to ensure data correctness under inherent high bit error rate caused by severe disturbance and interference in advanced high-density NAND flash memories. Then a multi-mode BCH ECC architecture was proposed to achieve high efficiency, low cost and low power consumption design of hybrid multi-channel high-capacity solid-state drives. Not only innovative ECC schemes, but also efficient hardware architecture was also presented to guarantee maximum bandwidth utilization for data transmission between a host system and NAND flash memory arrays no matter how slow the read/program/erase speed of a single NAND device is. In system performance, the development of wear-leveling, data caching, and flash block redundancy cover the degraded program and erase endurance of the advanced high-density NAND flash memory. Moreover, a CPRM (Content Protection for Recordable Media) implementation with associated hardware accelerators provides excellent data security but little extra overhead. Finally, hybrid non-volatile solid-state memory array architecture was proposed to provide the best cost/performance by benefiting from the advantages of kinds of non-volatile semiconductor memories, such as FeRAM (Ferroelectric RAM), MRAM (Magneto-resistive RAM), PRAM (Phase-change RAM) and high-density NAND flash memory. In summary, the proposed systematic design methodology together with the efficient controller architecture ensures that the cost, performance, reliability and lifetime of high-speed and high-capacity solid-state drives can meet the product specifications. The effectiveness and performance of the presented controller design are also proven through the chip implementation and experimental results.