标题: | 高速高容量固态硬碟机之控制晶片设计研究 On Study of Controller Chip Design for High-Speed and High-Capacity Solid-State Drives |
作者: | 林传生 Chuan-Sheng Lin 董兰荣 Lan-Rong Dung 电控工程研究所 |
关键字: | 固态硬碟机;非挥发性记忆体;错误更正码;快闪记忆体;Solid-State Drive;Non-volatile Memory;Error Correction Code;Flash Memory |
公开日期: | 2006 |
摘要: | 本论文主要针对固态硬碟机在使用高密度NAND型快闪记忆体时,因NAND型快闪记忆体的制程高度微缩与多层次(Multi-Level Cell)记忆技术所造成的性能劣化现象,而所必需要的控制晶片设计,提出了设计方法与电路架构。尤其是特别针对在高速高容量的固态硬碟机的控制晶片设计而言。近期,由于NAND型快闪记忆体密度的快速提升以及成本的下降,使得使用NAND型快闪记忆体的固态硬碟机来取代传统的硬式磁碟机,以作为可携式装置的资料存储设备成为极佳的选择。然而,如果欠缺了一个有效的控制晶片来处理这些高容量快闪记忆体的性能劣化问题,以及将整体系统的性能提升,则此固态硬碟机将会有使用上的限制,或者甚至有可能变成为无法使用的装置。在本论文中,针对了先进NAND快闪记忆体因为密度提高与MLC (Multi-Level Cell)技术所造成的资料读写与区块抹除的干扰因素增加,因而导致位元读写错误率的升高,提出了使用Systolic Array方法来构建 t-EC w-位元 并列式BCH (Bose-Chaudhuri-Hocquengham) ECC (Error-Correction Code)的硬体电路,来弥补这些性能劣化的现象,降低其位元读写错误率至一个可靠的水平。针对使用混合式多通道的快闪记忆体所构成的高速高容量固态硬碟机,提出了多模BCH ECC的电路架构,以提供一个高效率、低成本及低功率消耗的ECC电路架构。而对于对单一快闪记忆体晶片所能提供的资料读写速率极度有限,提出了高效能的资料传输硬体电路架构,以使主机系统与快闪记忆体阵列之间的资料传输效能达到系统所能提供的最高的频宽利用率。针对固态硬碟机里所存储的资料保全机制,提出了具硬体加速器方式的CPRM (Content Protection for Recordable Media)功能实施,以得到一个高效能且低成本的资料保全架构。在本论文中,我们提出混合式的多通道非挥发性固态记忆体所组成的固态硬碟机架构及其控制晶片设计,则具有能综合各种非挥发性记忆体之间的特性,而能达到整体固态硬碟机的最佳的成本与性能。这些非挥发性的固态记忆体中,除了NAND快闪记忆体之外,其他有如:FeRAM (Ferroelectric RAM), MRAM (Magneto-resistive RAM), PRAM (Phase-changed RAM)等。整体言之,本论文针对高速高容量固态硬碟机的控制晶片设计,提出了具体的电路设计方法与控制晶片的电路架构,使得一个合于产品规格的低成本、高资料传输率、高品质、寿命长的高速高容量固态硬碟机能具体的实施出来。并且,经由实际的晶片实作与测试,验证了这些方法与电路架构的有效性与优越的性能。 In this thesis, we present the key architectures of the controller chip design for solid-state drive. The key architectures of the controller chip were developed to cover the deficiencies of NAND Flash memory and to enhance the system performance, especially for the high-speed and high-capacity solid-state drive. Nowadays, the continuous price drop of NAND flash memory makes the solid-state drives affordable and a promising candidate to replace the hard disk drives in portables. However, the solid-state drives may become inefficient or even useless without the help of an intelligent controller chip, not to mention the fulfillment of high-speed and high-capacity. In this thesis, both innovative controller designs and circuit architectures were presented for solid-state drives to overcome the NAND flash device degradation caused by technology shrinking and thus improve the system performance of solid-state drives. A t-EC w-bit parallel BCH (Bose-Chaudhuri-Hocquengham) ECC (Error-Correction-Code) construction was first proposed to ensure data correctness under inherent high bit error rate caused by severe disturbance and interference in advanced high-density NAND flash memories. Then a multi-mode BCH ECC architecture was proposed to achieve high efficiency, low cost and low power consumption design of hybrid multi-channel high-capacity solid-state drives. Not only innovative ECC schemes, but also efficient hardware architecture was also presented to guarantee maximum bandwidth utilization for data transmission between a host system and NAND flash memory arrays no matter how slow the read/program/erase speed of a single NAND device is. In system performance, the development of wear-leveling, data caching, and flash block redundancy cover the degraded program and erase endurance of the advanced high-density NAND flash memory. Moreover, a CPRM (Content Protection for Recordable Media) implementation with associated hardware accelerators provides excellent data security but little extra overhead. Finally, hybrid non-volatile solid-state memory array architecture was proposed to provide the best cost/performance by benefiting from the advantages of kinds of non-volatile semiconductor memories, such as FeRAM (Ferroelectric RAM), MRAM (Magneto-resistive RAM), PRAM (Phase-change RAM) and high-density NAND flash memory. In summary, the proposed systematic design methodology together with the efficient controller architecture ensures that the cost, performance, reliability and lifetime of high-speed and high-capacity solid-state drives can meet the product specifications. The effectiveness and performance of the presented controller design are also proven through the chip implementation and experimental results. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT008712801 http://hdl.handle.net/11536/42890 |
显示于类别: | Thesis |
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