奈米點非揮發性記憶體元件之研究

Abstract

傳統的非揮發性記憶體是利用複晶矽浮停閘(floating gate)做為載子儲存的單元,當浮停閘儲存由通道注入的電子之後,元件的起始電壓就會發生改變,利用起始電壓的差異作為記憶體0和1邏輯的定義。然而,由於浮停閘是連續的一層半導體薄膜,在反覆的操作下,一旦穿隧氧化層(tunnel oxide)出現漏電路徑,儲存的電荷就會全部流失,記憶體就會失效,因此穿隧氧化層的厚度無法縮減下來,操作電壓無法降低,速度也無法增快。一般認為當元件通道長度達到65 nm時,便是此種結構的極限。本研究利用半導體或金屬奈米點作為電荷儲存的單元,可以減少穿隧氧化層的厚度,而不損失可靠性,進而降低操作電壓,並使元件縮小密度提高,操作速度增快。 利用半導體或金屬奈米點作為電荷儲存的單元。在元件的反覆操作下,即使穿隧氧化層產生缺陷或漏電路徑,所損失掉的儲存電子,僅是單一奈米點的電子漏失,對整體元件特性的影響並不明顯。因此,穿隧氧化層的厚度得以縮減,使得操作速度提升,元件積集度增加,元件可操作的次數(endurance)以及保存時間(retention)也同時得到改善。當電子儲存在奈米點時,由於庫倫阻絕(Coulomb blockade)效應,儲存的電子會限制後續電子的注入。奈米點的庫倫阻絕效應使得記憶體元件的儲存及操作更加的穩健。當閘極偏壓使通道產生反轉層後,通道的電子藉由直接穿隧效應或是F-N穿隧效應通過穿隧氧化層,而讓奈米點捕獲,是為寫入動作。當閘極偏壓反向時,儲存的電子便經由穿隧氧化層回到通道,是為抹除動作。藉由電容-電壓(C-V)量測,當電子注入奈米點之後,元件之起始電壓會發生偏移,此偏移的量即定義為記憶體元件的記憶窗。 本研究提出於穿隧氧化層上利用低壓化學氣相沈積(LPCVD)成長SiGe薄膜,並以熱氧化方式,使矽氧化成為二氧化矽作為控制氧化層,而鍺元素向下析出在穿隧氧化層上,作為載子儲存的單元。由穿透式電子顯微鏡圖(TEM)知,鍺奈米點析出於穿隧氧化層上,穿隧氧化層厚度約4.5奈米,鍺奈米點的尺寸大約5.5奈米,經由電性計算密度大約為4.2*1011/cm2。由圖中可估算,在5伏的操作電壓下,記憶窗大約有0.42伏,足夠作為記憶體定義0與1。然而當增加SiGe薄膜熱氧化時間，鍺便會氧化為氧化鍺，形成氧化鍺奈米點。經由電性量測後發現，氧化鍺奈米點也確實有記憶體特性，另外經由x-ray absorption near edge spectroscopy (XANES)也證實穿透式電子顯微鏡照片中的奈米點成分為氧化鍺，我們並且提出了一個物理模型來解釋此元件之記憶體效應。另外,在金屬奈米點方面,我們提出利用鉑金屬濺鍍於穿隧氧化層上,不需經過熱處理,自我組裝成核,鉑(Pt)奈米點的製作方式,藉由製程上的改進,可形成金屬奈米點並得到金屬奈米點的記憶體特性,並且在5伏的操作電壓下,達到0.25伏的起始電壓偏移(記憶窗) 。

In a conventional nonvolatile memory, charge is stored in a polysilicon floating gate (FG) surrounded by dielectrics. The scaling limitation stems from the requirement of very thin tunnel oxide layer. For FG, once the tunnel oxide develops a leaky path under repeated write/erase operation, all the stored charge will be lost. Therefore, the thickness of the tunnel oxide can not be scaled down to about 7 nm. To alleviate the scaling limitation of the conventional FG device while preserving the fundamental operating principle of the memory, we have studied the distributed charge storage approach such as the nanocrystal nonvolatile memory. Each nanodot will typically store only a handful of electrons; collectively the charges stored in these dots control the channel conductivity of the memory device. Nanocrystal charge storage offers several advantages, the main one being the potential to use thinner tunnel oxide without sacrificing nonvolatility. This is a quite attractive proposition since reducing the tunnel oxide thickness is a key to lowering operating voltages and/or increasing operating speeds. The improved scalability results not only from the distributed nature of the charge storage, which makes the storage more robust and fault-tolerant, but also from the beneficial effects of Coulomb blockade. A local leaky path will not cause a fatal loss of information for the nanocrystal nonvolatile memory device. Also, the nanocrystal memory device can maintain good retention characteristics and lower the power consumption. We have fabricated a nonvolatile memory device embedded with Ge nanocrystals by a thermal oxidation of Si0.8Ge0.2 combined with a rapid thermal annealing process. The tunnel oxide in the nonvolatile memory is 4.5 nm-thick and with 5.5-nm Ge nanocrystals reside on it. A low operating voltage, 5V, is implemented and a significant threshold-voltage shift, 0.42V, is observed. Also, we have demonstrated the novel distributed charge storage with GeO2 nano-dots. The mean size and aerial density of the dots are estimated to be about 5.5 nm and 4.3×1011 cm-2, respectively. The composition of the GeO2 dots is confirmed by the XANES measurements. In electrical analyses, a significant memory effect is observed with a threshold voltage shift of 0.45V under 5-V operation. Also, a physical model is proposed to explain the charge storage via the interfacial traps of GeO2 nano-dots. We have also proposed a simple process to fabricate metal nanocrystal memory which is one of the candidates that have great potential of achieving fast write/erase and long retention time simultaneously. Once the self-assembled nanocrystals have controllable density and size distribution, the metal nanocrystals can be incorporated into a standard MOSFET structure to fabricate nonvolatile memory devices.